IP Library Granted Patent US 10,013,194
Granted Patent B1
US 10,013,194 · App. 15/611,958 · Granted Jul 3, 2018

Handling thermal shutdown for memory devices

Inventors: Nian Niles Yang (Mountain View, CA); Varuna Kamila (San Jose, CA)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F3/0619G06F1/3206G06F3/0634G06F3/0647G06F3/0652G06F3/0653G06F3/0685
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Quick Facts
Patent No.
US 10,013,194
App. No.
15/611,958
Granted
Jul 3, 2018
Kind
B1
Abstract

The present disclosure discloses a memory device including a controller for handling thermal shutdown of the memory device. The control system acquires temperatures of a plurality of non-volatile memory elements in the memory device from one or more temperature detectors at a first frequency. Upon determining that the temperature of one of the plurality of non-volatile memory elements is above a threshold, the controller activates thermal throttling for the plurality of non-volatile memory elements and flushes metadata from a volatile memory element in the memory device to the plurality of non-volatile memory elements for future recovery of the memory device.

Claims (71)

1. A memory device, comprising:

a plurality of non-volatile memory elements configured to process a plurality of read/write operations;

a volatile memory element configured to store metadata of the memory device;

one or more temperature detectors configured to measure temperatures of the plurality of non-volatile memory elements; and

a controller configured to:

acquire the temperatures of the plurality of non-volatile memory elements from the one or more temperature detectors at a first frequency; and

upon determining that the temperature of a first one of the plurality of non-volatile memory elements is above a first threshold:

activate thermal throttling for the plurality of non-volatile memory elements; and

flush the metadata from the volatile memory element to the plurality of non-volatile memory elements.

2. A memory device, comprising:

a plurality of non-volatile memory elements configured to process a plurality of read/write operations;

a volatile memory element configured to store metadata of the memory device;

one or more temperature detectors configured to measure temperatures of the plurality of non-volatile memory elements; and

a controller configured to:

acquire the temperatures of the plurality of non-volatile memory elements from the one or more temperature detectors at a first frequency; and

upon determining that the temperature of a first one of the plurality of non-volatile memory elements is above a first threshold:

activate thermal throttling for the plurality of non-volatile memory elements; and

flush the metadata from the volatile memory element to the plurality of non-volatile memory elements wherein the metadata comprises one or more of:

Flash Translation Layer (FTL) logical block address (LBA) tables;

cell voltage distribution (CVD) tracking tables;

CVD caches;

XOR parity bins;

boot block updates;

file system block updates; and

block management tables.

3. A memory device, comprising:

a plurality of non-volatile memory elements configured to process a plurality of read/write operations;

a volatile memory element configured to store metadata of the memory device;

one or more temperature detectors configured to measure temperatures of the plurality of non-volatile memory elements; and

a controller configured to:

acquire the temperatures of the plurality of non-volatile memory elements from the one or more temperature detectors at a first frequency; and

upon determining that the temperature of a first one of the plurality of non-volatile memory elements is above a first threshold:

activate thermal throttling for the plurality of non-volatile memory elements; and

flush the metadata from the volatile memory element to the plurality of non-volatile memory elements wherein the controller is configured to flush the metadata from the volatile memory element to a plurality of control blocks in the plurality of non-volatile memory elements.

4. The memory device of claim 3 , wherein the plurality of control blocks comprises single level cell (SLC) control blocks.

5. The memory device of claim 3 , wherein the controller is configured to flush the metadata by writing the metadata to one or more pages in the plurality of control blocks at the first frequency.

6. A controller, comprising:

a processor;

a memory containing a program that, when executed on the processor, performs an operation, the operation comprising:

acquiring temperatures of a plurality of non-volatile memory elements in a memory device from one or more temperature detectors at a first frequency; and

upon determining that the temperature of a first one of the plurality of non-volatile memory elements is above a first threshold:

activating thermal throttling for the plurality of non-volatile memory elements; and

flushing metadata of the memory device from a volatile memory element in the memory device to the plurality of non-volatile memory elements.

7. A controller, comprising:

a processor;

a memory containing a program that, when executed on the processor, performs an operation, the operation comprising:

acquiring temperatures of a plurality of non-volatile memory elements in a memory device from one or more temperature detectors at a first frequency; and

upon determining that the temperature of a first one of the plurality of non-volatile memory elements is above a first threshold:

activating thermal throttling for the plurality of non-volatile memory elements; and

flushing metadata of the memory device from a volatile memory element in the memory device to the plurality of non-volatile memory elements wherein flushing metadata of the memory device comprises flushing the metadata from the volatile memory element to a plurality of control blocks in the plurality of non-volatile memory elements.

8. A controller, comprising:

a processor;

a memory containing a program that, when executed on the processor, performs an operation, the operation comprising:

acquiring temperatures of a plurality of non-volatile memory elements in a memory device from one or more temperature detectors at a first frequency; and

upon determining that the temperature of a first one of the plurality of non- volatile memory elements is above a first threshold:

activating thermal throttling for the plurality of non-volatile memory elements; and

flushing metadata of the memory device from a volatile memory element in the memory device to the plurality of non-volatile memory elements the operation further comprising setting a flag indicating the metadata in the plurality of control blocks.

9. The controller of claim 8 , further comprising setting the flag in a boot block in the plurality of non-volatile memory elements.

10. The controller of claim 8 , further comprising setting the flag after successfully flushing the metadata.

11. A method, comprising:

acquiring temperatures of a plurality of non-volatile memory elements in a memory device from one or more temperature detectors at a first frequency; and

upon determining that the temperature of a first one of the plurality of non-volatile memory elements is above a first threshold:

activating thermal throttling for the plurality of non-volatile memory elements; and

flushing metadata of the memory device from a volatile memory element in the memory device to the plurality of non-volatile memory elements.

12. The method of claim 11 , wherein the first frequency is determined by the memory device.

13. The method of claim 11 , further comprising:

upon determining that the temperature of a second one of the plurality of non-volatile memory elements is above a second threshold:

shutting down the memory device; and

recovering the memory device in a future power cycle issued by a host device based on the metadata in the plurality of non-volatile memory elements.

14. The method of claim 13 , wherein the second threshold is higher than the first threshold.

15. The method of claim 11 , wherein flushing metadata of the memory device comprises flushing the metadata upon determining that the temperature of the first non-volatile memory element is not decreased after activating the thermal throttling.

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2017
From: YANG, NIAN NILES; KAMILA, VARUNA
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 042571/0962 →
Cited By (3)
US 12,373,347 US 12,399,628 US 12,572,279