Active low-power termination
An active low-power termination circuit includes a first leg of a pair of transistors connected in series between the high supply level and ground, where the termination input is at a node between the transistors of the first node. A second leg uses a feed forward mechanism to control the voltage levels on the control gates of the transistors of the first leg. The second leg includes a second pair diode connected transistors, each of which is has its control gate connected to the control gate of the corresponding transistor in the first leg. A variable current source connected in series with the transistors of the second leg and is controlled by the output of a difference amplifier that has one input connect to an intermediate node of the second leg and a second input connected to a reference level intermediate to the high supply level and ground.
1. A semiconductor device comprising:
a first termination circuit, comprising:
a first leg including:
an input node;
a first transistor connected between a high voltage supply level and the input node; and
a second transistor connected between the input node and a low voltage supply level;
a second leg including:
an intermediate node;
a third transistor connected between the high voltage supply level and the intermediate node, the third transistor being diode connected and having a gate connected to a gate of the first transistor;
a fourth transistor connected between the intermediate node and the low voltage supply level, the fourth transistor being diode connected and having a gate connected to a gate of the second transistor; and
a variable current source connected in series with the third and fourth transistor between the high voltage supply level and the low voltage supply level; and
a difference amplifier having a first input connected to the intermediate node, a second input connected to a reference level intermediate to the high voltage supply level and low voltage supply level, and an output configured to control a current level through the variable current source based on the first input and the second input.
2. The semiconductor device of claim 1 , the first leg further including:
a fifth transistor through which the first transistor is connected to the high voltage supply level, the fifth transistor being diode connected; and
a sixth transistor through which the second transistor is connected to the low voltage supply level, the sixth transistor being diode connected.
3. The semiconductor device of claim 2 , the first termination circuit further comprising:
a seventh transistor having a gate connected to a gate of the fifth transistor; and
an eighth transistor having a gate connected to a gate of the sixth transistor, the seventh transistor and the eighth transistor connected in series between the high voltage supply level and the low voltage supply level and configured to supply an internal logic level voltage from a node between the seventh transistor and the eighth transistor.
4. The semiconductor device of claim 3 , the first termination circuit further comprising:
a first current source connected to the gate of the fifth transistor; and
a second current source connected to the gate of the sixth transistor.
5. The semiconductor device of claim 1 , wherein a strength of the first transistor, a strength of the second transistor, or the strengths of both of the first transistor and the second transistor is configurable.
6. The semiconductor device of claim 5 , wherein the second transistor comprises a plurality of devices selectively connectable in parallel between the input node and the low voltage supply level.
7. The semiconductor device of claim 1 , the second leg further including:
a resistor through which the fourth transistor is connected to the low voltage supply level.
8. The semiconductor device of claim 7 , wherein a resistance value of the resistor is configurable.
9. The semiconductor device of claim 1 , wherein the first and third transistors are NMOS devices and the second and fourth transistors are PMOS devices.
10. The semiconductor device of claim 1 , wherein the variable current source is connected between the third transistor and the high voltages supply level.
11. The semiconductor device of claim 1 , wherein the semiconductor device is a memory circuit comprising:
a first bond pad configured to exchange electrical signals with a first bond wire connected thereto, the input node of the first termination circuit connected to the first bond pad.
12. The semiconductor device of claim 11 , further comprising:
a second bond pad configured to exchange electrical signals with a second bond wire connected thereto; and
a second termination circuit, including:
a node connected to the second bond pad;
a fifth transistor connected between the high voltage supply level and the node connected to the second bond pad, a gate of the fifth transistor connected to the gate of the third transistor; and
a sixth transistor connected between the node connected to the second bond pad and ground, a gate of the sixth transistor connected to the gate of the fourth transistor.
13. A memory package, comprising:
a plurality of non-volatile memory circuits;
a package board on which the plurality of non-volatile memory circuits are mounted;
a bus structure connecting the non-volatile memory circuits; and
an active termination circuit formed on one of the non-volatile memory circuits and connected to the bus structure, the active termination circuit comprising:
a first leg including a first transistor and a second transistor connected in series between a high voltage supply level and ground, the bus structure connected to a node between the first and second transistors; and
a second leg including a third transistor and a fourth transistor connected in series between the high voltage supply level and ground, and including a difference amplifier configured to maintain a node between the third and fourth transistors at a reference voltage intermediate to the high voltage supply level and ground, the second leg connected to first leg and configured to bias the first transistor and the second transistor based on bias conditions on the third transistor and the fourth transistor.
14. The memory package of claim 13 , further comprising:
a controller mounted on the package board and connected to the bus structure.
15. The memory package of claim 13 , wherein the memory package is configured to be mounted on a printed circuit board including a controller and the bus structure configured to be connected to the controller.
16. A system, comprising:
a first integrated circuit;
a second integrated circuit;
an interconnect configured to transmit signals between the first integrated circuit and the second integrated circuit; and
an active termination circuit formed on one of either the first integrated circuit and the second integrated circuit and connected to the interconnect, the active termination circuit comprising:
a first leg including a first transistor and a second transistor connected in series between a high voltage supply level and ground, the interconnect connected to a node between the first and second transistors; and
a second leg including a third transistor and a fourth transistor connected in series between the high voltage supply level and ground, and including a difference amplifier configured to maintain a node between the third and fourth transistors at a reference voltage intermediate to the high voltage supply level and ground, the second leg connected to first leg and configured to bias the first transistor and the second transistor based on bias conditions on the third transistor and the fourth transistor.
17. The system of claim 16 , wherein the first integrated circuit and the second integrated circuit are mounted on a printed circuit board.
18. The system of claim 16 , wherein the first integrated circuit is a non-volatile memory circuit and the second integrated circuit is a non-volatile memory controller circuit.
19. The system of claim 18 , wherein the system is part of a memory card.
20. The system of claim 18 , wherein the system is part of a solid state drive (SSD).