SSD wafer device and method of manufacturing same
A solid state drive (SSD) wafer device includes first and second semiconductor wafers coupled together. The first wafer may include a number of memory dies with die bond pads, and the second wafer may include a number of electrical interconnects, each including first and second terminals at opposed ends of the electrical interconnect. When the wafers are bonded together, the first terminals of the second wafer are bonded to the die bond pads of the memory dies of the first wafer. The second terminals are left exposed to couple with an SSD controller, which controls the transfer of data and signals between the memory dies of the first wafer and a host device such as a server in a datacenter.
1. A solid state drive (SSD) wafer device, comprising:
a first semiconductor wafer comprising first and second major surfaces, a plurality of memory dies, each memory die of the plurality of memory dies comprising a plurality of bond pads at the first major surface, and one or more cutouts; and
a second semiconductor wafer comprising third and fourth major surfaces, and a plurality of electrical interconnects, each electrical interconnect comprising a first terminal at the third major surface, at a first end of the electrical interconnect, and a second terminal at the third major surface, at a second end of the electrical interconnect opposite the first end, the second terminal of each of the electrical interconnects configured to transfer signals between the second semiconductor wafer and an external device;
wherein the first major surface of the first semiconductor wafer is coupled to the third major surface of the second semiconductor wafer, with the first terminal of each of the plurality of electrical interconnects bonded to a die bond pad of the plurality of die bond pads and the second terminal of each of the plurality of electrical interconnects positioned in the one or more cutouts.
2. The SSD wafer device of claim 1 , wherein the one or more cutouts comprise a plurality of cutouts are positioned around a periphery of the first semiconductor wafer.
3. The SSD wafer device of claim 1 , further comprising one or more SSD controllers electrically coupled to the second terminals of the plurality of electrical interconnects.
4. The SSD wafer device of claim 3 , wherein at least one of the one or more SSD controllers is physically positioned within the one or more cutouts.
5. The SSD wafer device of claim 4 , wherein the at least one SSD controller is flip-chip bonded to the second terminal of at least some of the plurality of electrical interconnects.
6. The SSD wafer device of claim 1 , further comprising:
a plurality of signal/data connectors directly coupled to the second terminals of the plurality of electrical interconnects; and
an SSD controller coupled to the plurality of signal/data connectors to transfer one or both of signals and data to and from the second terminals of the plurality of electrical interconnects.
7. The SSD wafer device of claim 6 , wherein the SSD controller comprises a master SSD controller, and the plurality of signal/data connectors comprise SSD controllers coupled to the master SSD controller.
8. A solid state drive (SSD) wafer device, comprising:
a first semiconductor wafer comprising first and second major surfaces, a plurality of memory dies, each memory die comprising a plurality of bond pads at the first major surface, and one or more cutouts;
a second semiconductor wafer bonded to the first semiconductor wafer, the second semiconductor wafer comprising third and fourth major surfaces, and a plurality of electrical interconnects, each electrical interconnect comprising a first terminal at the third major surface, at a first end of the electrical interconnect, and a second terminal at the third major surface, at a second end of the electrical interconnect opposite the first end, the first terminal of each of the plurality of electrical interconnects bonded to a die bond pad of the plurality of die bond pads; and
one or more SSD controllers positioned in the one or more cutouts and electrically coupled to the second terminals of the plurality of electrical interconnects.
9. The SSD wafer device of claim 8 , wherein at least one SSD controller of the one or more SSD controllers comprises bond pads that are directly coupled to the second terminals of the plurality of electrical interconnects.
10. The SSD wafer device of claim 8 , wherein the one or more cutouts comprise at least one cutout at a periphery of the first semiconductor wafer.
11. The SSD wafer device of claim 10 , wherein the second terminals of the plurality of electrical interconnects terminate at the third major surface of the second semiconductor wafer at positions corresponding to the at least one cutout when the first and second semiconductor wafer are coupled together.
12. A solid state drive (SSD) wafer device, comprising:
a first semiconductor wafer comprising first and second major surfaces, a plurality of NAND dies, each NAND die of the plurality of NAND dies comprising a plurality of bond pads at the first major surface, and one or more cutouts;
a second semiconductor wafer coupled to the first semiconductor wafer, the second semiconductor wafer comprising third and fourth major surfaces, and electrical interconnect means comprising first ends at the third major surface and second ends at the third major surface;
wherein the first and second wafers are bonded together such that the first ends of the electrical interconnect means are electrically coupled to the die bond pads of the plurality of die bond pads and the second ends of the electrical interconnect means positioned within the one or more cutouts.