Memory apparatus for early write termination and power failure
View Patent ↗In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.
1. A memory apparatus comprising:
a base printed circuit board (PCB) having an edge connector for plugging into a host server system to receive host power;
a card level power source mounted to the base PCB to provide card level power during a power failure;
one or more memory controllers coupled to the card level power source, each of the one or more memory controllers having a plurality of memory channels;
a plurality of non-volatile memory devices (NVMDs) coupled to the card level power source and organized to couple to the plurality of memory channels of the one or more memory controllers;
wherein each of the one or more memory controllers to provide queuing and scheduling of memory operations on a channel for each NVMD in the channel, wherein each of the one or more memory controllers includes
one or more channel controllers each having a scheduler to control the queuing and scheduling of memory operations to the NVMDs in the channel;
wherein in response to a power failure to the host server system or the host power to the edge connector, the one or more memory controllers to receive card level power and change the scheduling of memory operations to the plurality of NVMDs in the plurality of memory channels.
2. The memory apparatus of claim 1 , wherein
the card level power source is a plurality of high density power capacitors.
3. The memory apparatus of claim 1 , wherein
the card level power source is a battery.
4. The memory apparatus of claim 1 , wherein in response to a power failure to the host server system or the host power to the edge connector,
the plurality of NVMDs in the plurality of memory channels receive the card level power, and
the one or more memory controllers reprioritize the schedule of memory operations to first complete any pending write operations with the plurality of NVMDs in the plurality of memory channels and then complete any delayed write operations with the plurality of NVMDs in the plurality of memory channels.
5. The memory apparatus of claim 1 , further comprising:
a power failure circuit coupled to the edge connector and the card level power source,
wherein if the power failure circuit detects a power failure in the host power at the edge connector, it switches from the host power over to the card level power and supplies the card level power to the one or more memory controllers and the plurality of NVMDs in the plurality of memory channels.
6. The memory apparatus of claim 5 , wherein
the card level power source is a plurality of high density power capacitors, and
the power failure circuit switches to the host power at the edge connector to charge up the plurality of high density power capacitors so they are ready to supply the card level power during a power failure.
7. The memory apparatus of claim 5 , wherein
the card level power source is a rechargeable battery, and
the power failure circuit switches to the host power at the edge connector to charge up the rechargeable battery so that it is ready to supply the card level power during a power failure.
8. The memory apparatus of claim 1 , wherein
if a delayed write operation is stored for an NVMD, the scheduler prevents other operations from being executed with the NVMD having the delayed write operation.
9. The memory apparatus of claim 1 , wherein
if a delayed write operation is stored for an NVMD, the scheduler permits a limited set of operations to be executed with the NVMD having the delayed write operation.
10. The memory apparatus of claim 9 , wherein
the limited set of operations comprises a read operation.
11. The memory apparatus of claim 9 , wherein
prior to executing the delayed write operations, the channel controller completes any currently executing operations with the NVMD having the delayed write operation.
12. The memory apparatus of claim 1 , wherein in the event of a power failure,
a power capacity of a card level power source supplying the card level power is sufficient to complete execution of one or more delayed write operations with one or more NVMDs.
13. A memory apparatus comprising:
a base printed circuit board (PCB) having an edge connector for plugging into a host server system to receive host power;
a card level power source mounted to the base PCB to provide card level power during a power failure;
one or more memory controllers coupled to the card level power source and having one or more memory channels;
one or more non-volatile memory devices (NVMDs) coupled to the card level power source, the one or more NVMDs organized to respectively couple to the one or more memory channels of the one or more memory controllers;
wherein each of the one or more memo controllers to provide queuing and scheduling of memory operations on a channel for each NVMD in the one or more memory channels, and each memory controller includes
one or more channel controllers to control the queuing and scheduling of memory operations to the one or more NVMDs in the channel, each of the one or more channel controllers including one or more backup location registers associated with each NVMD in the channel;
a shared buffer pool coupled to the one or more channel controllers, the storage locations of the shared buffer pool shared amongst the one or more channel controllers; and
wherein in response to a failed write of data from a first location in the shared buffer pool to a first NVMD address, the channel controller to rewrite the data from the first location into a first NVMD backup address pointed to by a first backup location register;
and
wherein in response to a power failure to the host server system or the host power to the edge connector, the one or more memory controllers to receive card level power and change the scheduling of memory operations to the one or more NVMDs in each of the one or more memory channels.
14. The memory apparatus of claim 13 , wherein
in response to a successful write of data from the first location to the first NVMD backup address, the channel controller to provide an indicator that the write of data was successful and data was stored into the first NVMD backup address.
15. The memory apparatus of claim 14 , wherein
in response to the successful write of data using the first NVMD backup address pointed to by the first backup location register, the first backup location register is replenished with a new NVMD address differing from the first NVMD backup address into which a data write operation can be absorbed.
16. The memory apparatus of claim 13 , wherein
during a power failure, a power capacity of a card level power source supplying the card level power is sufficient to support attempts of the rewrite of data from the first location into the first NVMD backup address.
17. The memory apparatus of claim 13 , wherein
in response to a failed write of data from the first location to the first NVMD backup address, the channel controller to rewrite the data from the first location into a second NVMD backup address pointed to by a second backup location register.
18. The memory apparatus of claim 17 , wherein
in response to a successful write of data from the first location to the second NVMD backup address, the channel controller to provide an indicator that the write of data was successful and data was stored into the second NVMD backup address.
19. The memory apparatus of claim 18 , wherein
in response to the successful write of data using the second NVMD backup address pointed to by the second backup location register, the first and second backup location registers are replenished with new NVMD addresses differing from the second and second NVMD backup addresses into which data write operations can be absorbed.
20. The memory apparatus of claim 17 , wherein
during a power failure, a power capacity of a card level power source supplying the card level power is sufficient to support attempts of the rewrite of data from the first location into the first NVMD backup address, and the rewrite of data from the first location into the second NVMD backup address.
21. The memory apparatus of claim 17 , wherein
in response to a failed write of data from the first location to the second NVMD backup address, the channel controller to rewrite the data from the first location into a third NVMD backup address pointed to by a third backup location register.
22. The memory apparatus of claims 21 , wherein
in response to a successful write of data from the first location to the third NVMD backup address, the channel controller to provide an indicator that the write of data was successful and data was stored into the third NVMD backup address.
23. The memory apparatus of claim 22 , wherein
in response to the successful write of data using the third NVMD backup address pointed to by the third backup location register, the first, second, and third backup location registers are replenished with new NVMD addresses differing from the second, third, and third NVMD backup addresses into which data write operations can be absorbed.
24. The memory apparatus of claim 21 , wherein
during a power failure, a power capacity of a card level power source supplying the card level power is sufficient to support attempts of the rewrite of data from the first location into the first NVMD backup address, the rewrite of data from the first location into the second NVMD backup address, and the rewrite of data from the first location into the third NVMD backup address.
25. The memory apparatus of claim 21 , wherein
the channel controller further to write the first NVMD address into an NVMD along with the write data.
26. The memory apparatus of claim 17 , wherein
the channel controller further to write the first NVMD address into an NVMD along with the write data.
27. The memory apparatus of claim 13 , wherein
the channel controller further to write the first NVMD address into an NVMD along with the write data.
28. The memory apparatus of claim 27 , wherein
the NVMD is a NAND flash memory;
the write operation corresponds to writing of a NAND flash write page; and
the first NVMD address is written into the spare area associated with the NAND flash write page.
29. The memory apparatus of claim 27 , wherein
during a post power failure recovery, address locations in the NVMDs are examined corresponding to the addresses stored in the backup location registers prior to power failure to determine if any have been used, and if so, the first NVMD address whose write failure triggered the use of the NVMD backup address is determined.
30. A memory apparatus comprising:
a base printed circuit board (PCB) having an edge connector for plugging into a host server system to receive host power;
a card level power source mounted to the base PCB to provide card level power during a power failure;
one or more memory controllers coupled to the card level power source and having one or more memory channels;
one or more non-volatile memory devices (NVMDs) coupled to the card level power source, the one or more NVMDs organized to respectively couple to the one or more memory channels of the one or more memory controllers;
wherein each of the one or more memo controllers to provide queuing and scheduling of memory operations on a channel for each NVMD in the one or more memory channels, and each memory controller includes
one or more channel controllers to control the queuing and scheduling of memory operations to the one or more NVMDs in the channel, each of the one or more channel controllers including at least one register per NVMD to store delayed write operations for the respective NVMD;
a shared buffer pool coupled to the one or more channel controllers, the shared buffer pool including at least one delayed write buffer per NVMD coupled to the channel, the at least one delayed write buffer to store the write data associated with the delayed write operations stored in the set of the plurality of registers; and
wherein in response to a power failure, the channel controller to execute the delayed write operations for each NVMD stored in the at least one register writing the data from the at least one delayed write buffer into the NVMD;
and
wherein in response to a power failure to the host server system or the host power to the edge connector, the one or more memory controllers to receive card level power and change the scheduling of memory operations to the one or more NVMDs in each of the one or more memory channels.
31. The memory apparatus of claim 30 , wherein
each of the one or more channel controllers further includes a scheduler to control the queuing and scheduling of memory operations to the NVMDs in the channel.
32. The memory apparatus of claim 31 , wherein
if a delayed write operation is stored for an NVMD, the scheduler prevents other operations from being executed with the NVMD having the delayed write operation.
33. The memory apparatus of claim 31 , wherein
if a delayed write operation is stored for an NVMD, the scheduler permits a limited set of operations being executed with the NVMD having the delayed write operation.
34. The memory apparatus of claim 33 , wherein
the limited set of operations comprises a read operation.
35. The memory apparatus of claim 33 , wherein
prior to executing the delayed write operations, the channel controller completes any currently executing operations with the NVMD having the delayed write operation.
36. The memory apparatus of claim 35 , wherein
during a power failure, a power capacity of a card level power source supplying the card level power is sufficient to complete execution of any of the currently executing operations with NVMDs and to further complete execution of all the delayed write operations stored in the at least one register of each channel controller of the one or more memory controllers.
37. The memory apparatus of claim 30 , wherein
during a power failure, a power capacity of a card level power source supplying the card level power is sufficient to complete execution of all the delayed write operations stored in the at least one register of each channel controller of the one or more memory controllers.
38. The memory apparatus of claim 30 , wherein
each of the channel controllers further includes one or more backup location registers associated with each NVMD in the channel; and
wherein in response to a failed delayed write operation from a first delayed write buffer location in the shared buffer pool to a first NVMD address, the channel controller to rewrite the data from the first delayed write buffer location into a first NVMD backup address pointed to by a first backup location register.