IP Library Granted Patent US 11,043,537
Granted Patent B2
US 11,043,537 · App. 16/440,250 · Granted Jun 22, 2021

Three-dimensional phase change memory device including vertically constricted current paths and methods of manufacturing the same

Inventors: Yuji Takahashi (San Jose, CA); Masatoshi Nishikawa (Nagoya, JP); Wei Kuo Shih (Cupertino, CA)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
H01L27/249H01L27/2427H01L45/06H01L45/1683
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Quick Facts
Patent No.
US 11,043,537
App. No.
16/440,250
Granted
Jun 22, 2021
Kind
B2
Abstract

An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack. Protruding tip portions are formed on each of the sacrificial material layers around the memory openings. A plurality of insulating spacers is formed within each memory opening between each vertically neighboring pair of tip portions of the sacrificial material layers. A phase change memory material and a vertical bit line are formed within each of the memory openings. The phase change memory material can be formed as a vertical stack of discrete annular phase change memory material portions, or can be formed as a continuous phase change memory material layer. Each of the sacrificial material layer can be replaced by an electrically conductive layer.

Claims (16)

1. A three-dimensional memory device comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate; and

memory openings extending through the alternating stack and filled within a respective memory opening fill structure,

wherein:

each memory opening fill structure comprises a vertical bit line and a vertical stack of discrete phase change memory material portions;

each of the discrete phase change memory material portions in the vertical stack is located between a respective vertically neighboring pair of the insulating layers within the alternating stack and has a vertical thickness that is less than a vertical thickness of a respective electrically conductive layer located between the respective vertically neighboring pair of the insulating layers within the alternating stack; and

each memory opening fill structure comprises a vertical stack of spacers; and

a plurality of spacers within the vertical stack of spacers contacts a sidewall, a portion of a top surface, and a portion of a bottom surface, of a respective one of the insulating layers within the alternating stack.

2. The three-dimensional memory device of claim 1 , wherein each spacer within the plurality of spacers contacts a bottom surface of an overlying one of the discrete phase change memory material portions and contacts a top surface of an underlying one of the discrete phase change memory material portions.

3. The three-dimensional memory device of claim 2 , wherein each interface between the plurality of spacers and the discrete phase change memory material portions is an annular interface located within a respective horizontal plane.

4. The three-dimensional memory device of claim 1 , wherein each spacer within the plurality of spacers comprises:

an upper annular convex surface having a bottom periphery that contacts the top surface of the respective one of the insulating layers within the alternating stack; and

a lower annular convex surface having a top periphery that contacts the bottom surface of the respective one of the insulating layers within the alternating stack.

5. The three-dimensional memory device of claim 1 , wherein a spacer among the plurality of spacers comprises:

an annular top surface having an inner periphery that is adjoined to an upper periphery of a vertical cylindrical sidewall of the spacer; and

an annular bottom surface having an inner periphery that is adjoined to a lower periphery of the vertical cylindrical sidewall of the spacer.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 13, 2019
From: TAKAHASHI, YUJI; NISHIKAWA, MASATOSHI; SHIH, WEI KUO
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 049461/0227 →
Cited By (4)
US 12,255,242 US 12,362,301 US 12,563,973 US 12,581,665