Granted Patent B2

US 10,727,867 · App. 16/021,857 · Granted Jul 28, 2020

Abstract

Claims (89)

1. An apparatus, comprising:

a storage media configured to store encoded data;

a cache memory configured to store information relating to errors, comprising at least one error location index indicating decoding error location information relating to at least a portion of the encoded data, resultant from decoding one or more prior read operations directed to the encoded data; and

a decoder configured to decode the encoded data retrieved from the storage media, the decoding augmented by the information relating to the errors.

2. The apparatus of claim 1 , wherein the decoder is further configured to:

augment decoding of the encoded data by at least initializing reliability parameters in a low-density parity-check (LDPC) scheme with the error location information indicated in the at least one error location index.

3. The apparatus of claim 1 , wherein the decoder is further configured to:

determine further error location information resultant from decoding the encoded data; and

based at least on the further error location information differing from the at least one error location index, update the at least one error location index with the further error location information.

4. The apparatus of claim 3 , wherein the decoder is further configured to:

retrieve checksum data computed for the at least one error location index; and

compare the checksum data to new checksum data computed for the further error location information to determine when the further error location information differs from the at least one error location index.

5. The apparatus of claim 1 , wherein the information relating to the errors comprises at least parity bits computed responsive to decoding the one or more prior read operations; and

wherein the decoder is further configured to:

retrieve the parity bits from the cache memory; and

augment the decoding of the encoded data using at least the parity bits to add one or more error correcting elements in a low-density parity-check (LDPC) scheme.

6. The apparatus of claim 5 , further comprising:

a read scrubber configured to extend a read scrub threshold for the storage media based at least on the parity bits.

7. An apparatus, comprising:

a storage media comprising a read enhanced portion;

a host interface; and

a storage controller configured to:

receive read operations over the host interface directed to the read enhanced portion of the storage media;

configure decode parameters for the read operations based at least on errors resultant from decoding one or more prior read operations directed to the read enhanced portion; and

decode data retrieved from the read enhanced portion of the storage media.

8. The apparatus of claim 7 , wherein the storage controller is configured to configure the decode parameters based on an error vector comprising error locations resultant from the one or more prior read operations directed to the read enhanced portion.

9. The apparatus of claim 8 , wherein the storage controller is configured to maintain the error vector in a cache memory separate from the storage media.

10. The apparatus of claim 8 , wherein the storage controller is configured to compare checksum data for the error vector to new checksum data computed for the error vector updated to reflect bit errors from a present decode to determine when to update the error vector.

11. The apparatus of claim 8 , wherein the storage controller is configured to aid decode of the data by at least initializing reliability decode parameters for a low-density parity-check (LDPC) decoding scheme using the error locations indicated in the error vector.

12. The apparatus of claim 7 , wherein the storage controller is configured to compute and store parity bits responsive to a quantity of the errors resultant from decoding the one or more prior read operations exceeding an error threshold.

13. The apparatus of claim 12 , comprising:

the storage controller configured to store the parity bits from a cache memory separate from the storage media.

14. The apparatus of claim 12 , comprising:

the storage controller configured to extend a read scrub threshold for the read enhanced portion of the storage media based at least on the parity bits.

15. A method, comprising:

retrieving a first encoded data segment stored on a storage media;

computing information relating to errors, comprising an indication of error locations resultant from decoding the first encoded data segment;

storing the information relating to the errors in a cache;

retrieving a second encoded data segment stored on the storage media;

configuring a decoding engine using at least the information relating to errors retrieved from the cache; and

decoding the second encoded data with the decoding engine to produce resultant data.

16. The method of claim 15 ,

further comprising:

initializing reliability parameters for a low-density parity-check (LDPC) function of the decoding engine using the indication of the error locations.

17. The method of claim 15 , wherein the information comprises parity bits computed responsive to a quantity of the errors resultant from decoding the first encoded data segment exceeding an error threshold; and

further comprising:

retrieving the parity bits from the cache; and

configuring the decoding engine with the parity bits.

18. The method of claim 17 , further comprising:

extending an error threshold for a read scrub procedure for the storage media based at least on the parity bits.

19. A storage device, comprising:

a storage media configured to store encoded data;

a host interface configured to receive read requests for data stored by the storage device;

a cache memory configured to store an error vector; and

a storage controller configured to:

retrieve first encoded data from the storage media responsive to a first read request;

decode the first encoded data and identify resultant error locations;

update the error vector with the resultant error locations;

configure an error correction decoder using the error vector;

retrieve second encoded data from the storage media responsive to a second read request;

decode the second encoded data into decoded data with the error correction decoder; and

transfer the decoded data over the host interface.

20. The storage device of claim 19 , wherein the storage controller is configured to supplement parity bits included in the second encoded data with at least parity bits computed based on resultant error locations of the first encoded data.

21. The storage device of claim 19 , wherein the storage controller is configured to initialize reliability parameters for a low-density parity-check (LDPC) function of the error correction decoder with the resultant error locations.

22. The storage device of claim 19 , wherein the storage controller is configured to:

compare checksum data computed for the error vector stored in the cache memory to new checksum data computed for error locations resultant from decoding the second encoded data; and

based at least on a difference indicated by the comparison, update the error vector to reflect bit errors and store the new checksum data in the cache memory.

23. A data error corrector, comprising:

means for generating information relating to errors resultant from decoding at least an initial encoded data segment with a decoding scheme;

means for revising the decoding scheme based at least in part on the information;

means for decoding a subsequent encoded data segment into a decoded data segment with the revised decoding scheme;

means for transmitting the decoded data segment; and

means for selecting among at least one of a first augmentation operation and a second augmentation operation for revising the decoding scheme;

wherein:

the first augmentation operation comprises supplementing parity bits included in the subsequent encoded data segment with at least parity bits computed for the initial encoded data segment;

the second augmentation operation comprises initializing reliability parameters for the decoding scheme using an error vector that indicates error locations resultant from decoding at least the initial encoded data segment with the decoding scheme.

24. An apparatus, comprising:

a storage media configured to store encoded data;

a cache memory configured to store information relating to errors, comprising at least parity bits computed responsive to decoding one or more prior read operations directed to the encoded data; and

a decoder configured to:

retrieve the parity bits from the cache memory, and

decode the encoded data retrieved from the storage media, the decoding augmented by using at least the parity bits to add one or more error correcting elements in a low-density parity-check (LDPC) scheme.

25. A method, comprising:

retrieving a first encoded data segment stored on a storage media;

computing information relating to errors, comprising parity bits computed responsive to a quantity of the errors resultant from decoding the first encoded data segment exceeding an error threshold;

storing the information relating to the errors in a cache;

retrieving a second encoded data segment stored on the storage media;

configuring a decoding engine using at least the information relating to errors retrieved from the cache; and

decoding the second encoded data with the decoding engine to produce resultant data.

Assignments (10)