Data storage device with weak bits handling
A data storage device includes a non-volatile memory device that includes at least a first wordline having first data and a second wordline sequential and adjacent to the first wordline and a controller coupled to the non-volatile memory device. The controller is configured to receive a write command to program second data to the second wordline, read and store the first data from the first wordline a in a first location prior to programming the second data, program the second data to the second wordline, re-read and store the first data from the first wordline in a second location during the programming, compare the read first data and the re-read first data, and mark one or more bits of the first wordline that are different based on the comparing. The marked one or more bits are used as soft bits in future read and decode operations.
1. A data storage device, comprising:
a non-volatile memory device comprising at least a first wordline and a second wordline, wherein the second wordline is sequential and adjacent to the first wordline, and wherein the first wordline comprises first data;
a volatile memory device; and
a controller coupled to the non-volatile memory device and the volatile memory device, wherein the controller is configured to:
receive a write command to program second data to the second wordline;
prior to programming the second data to the second wordline, read the first data from the first wordline and store the read first data in a first location of the volatile memory device, wherein the read first data comprises a plurality of first bits;
program the second data to the second wordline;
during the programming, re-read the first data from the first wordline and store the re-read first data in a second location of the volatile memory device, wherein the re-read first data comprises a plurality of second bits;
compare the plurality of first bits from the first location of the volatile memory device to the plurality of second bits from the second location of the volatile memory device to identify one or more bits of the plurality of first bits that are different from one or more bits of the plurality of second bits;
mark the one or more bits that are different; and
read and decode the marked one or more bits.
2. The data storage device of claim 1 , wherein the first location and the second location are distinct.
3. The data storage device of claim 1 , wherein the controller is further configured to, when re-programming the first wordline, not program the marked one or more bits.
4. The data storage device of claim 1 , wherein programming the second data to the second wordline comprises sending a number of program pulses to the second wordline, and wherein the number of program pulses equals a number of cell states of a cell comprising the first wordline and the second wordline.
5. The data storage device of claim 4 , wherein the controller is further configured to perform a verify operation after each program pulse of the number of program pulses.
6. The data storage device of claim 4 , wherein the controller is further configured to identify that the programming the second data is near completion, wherein the identifying comprises:
determining a number of cells of the second wordline that has not yet been programmed; and
determining a difference between the number of cells of the second wordline that has not yet been programmed and a total number of cells of the second wordline.
7. The data storage device of claim 6 , wherein the re-reading occurs when the difference is less than or equal to a threshold number of cells.
8. The data storage device of claim 4 , wherein the controller is further configured to identify that the programming the second data is near completion, wherein the identifying comprises:
determining an index of a current programming pulse; and
determining a difference between the index of the current programming pulse and the number of program pulses to the second wordline.
9. The data storage device of claim 8 , wherein the re-reading occurs when the difference is less than or equal to a threshold number of program pulses.
10. The data storage device of claim 1 , wherein the marked one or more bits are stored either in a random access memory device or double data rate memory device.
11. The data storage device of claim 10 , wherein the controller is further configured to:
receive a read command for the first wordline;
retrieve the stored marked one or more bits; and
utilize the retrieved stored marked one or more bits in a decoding operation for the read command for the first data of the first wordline.
12. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
receive a write command for a wordline of the memory device;
read a previously programmed wordline of the memory device, wherein the previously programmed wordline is adjacent to the wordline;
store the read previously programmed wordline in a first buffer in volatile memory;
execute the write command for the wordline;
during the executing, re-read the previously programmed wordline;
store the re-read previously programmed wordline in a second buffer in the volatile memory;
determine that one or more bits of the stored read previously programmed wordline that is in the first buffer in the volatile memory are different than the stored re-read previously programmed wordline that is in the second buffer in the volatile memory to identify one or more bits of the stored read previously programmed wordline that are different from one or more bits of the stored re-read previously programmed wordline;
mark the one or more bits that are different;
read and decode the marked one or more bits; and
store a location of the marked one or more bits in a volatile memory device of the data storage device, wherein the marked one or more bits are used as soft bits, wherein the soft bits are read and provided to a decoder for decode operations.
13. The data storage device of claim 12 , wherein the volatile memory device is disposed in the controller.
14. The data storage device of claim 12 , wherein the controller is further configured to utilize the location during a decoding operation of the previously programmed wordline.
15. The data storage device of claim 12 , wherein the marked one or more bits indicates that the one or more bits that are affected by a program disturb due to executing the write command.
16. The data storage device of claim 12 , wherein the marked one or more bits indicates that the one or more bits lost charge during the executing the write command.
17. The data storage device of claim 12 , wherein the controller is configured to generate additional error correction code for data programmed to the location corresponding to the marked one or more bits.
18. A data storage device, comprising:
non-volatile memory means;
volatile memory means; and
a controller coupled to the non-volatile memory means and the volatile memory means, wherein the controller comprises a flash state machine, and wherein the flash state machine is configured to:
receive a write command to write second data to a second wordline, wherein the second wordline is sequential and adjacent to a first wordline;
read first data of the first wordline for a first time and store the read first data from the first time in the volatile memory means;
program the second write data to the second wordline;
read the first data of the first wordline for a second time and store the read first data from the second time in the volatile memory means;
compare the first data read for the first time from the volatile memory means to the first data read for the second time from the volatile memory means to identify one or more bits of the first data read for the first time that are different from one or more bits of the first data read of the second time;
mark the one or more bits that are different;
read and decode the marked one or more bits; and
store a location of the marked one or more bits in the volatile memory means, wherein the marked one or more bits are used as soft bits, wherein the soft bits are read and provided to a decoder for decode operations.
19. The data storage device of claim 18 , wherein the reading the first data of the first wordline for the second time occurs during programming the second write data to the second wordline.
20. The data storage device of claim 18 , wherein:
the first data read for the first time is stored in a first location of the volatile memory means;
the first data read for the second time is stored in a second location of the volatile memory means; and
the first location and the second location are distinct.