Temperature compensation management in solid-state memory
View Patent ↗Systems and methods are disclosed for programming data in a non-volatile memory array are disclosed. A data storage device includes a non-volatile memory array including a plurality of non-volatile memory cells and a controller configured to receive a signal indicating a temperature of at least a portion of the data storage device. The controller determines a first offset program verify level associated with a first programming level based at least in part on the temperature and programs a first set of the memory cells of the non-volatile memory array using the first offset program verify level.
1. A data storage device comprising:
a non-volatile memory array including a plurality of non-volatile memory cells; and
a controller configured to:
receive a signal indicating a temperature of at least a portion of the data storage device;
determine a first offset program verify level associated with a first programming level based at least in part on the temperature;
determine a second offset program verify level associated with a second programming level based at least in part on the temperature;
program a first set of the memory cells of the non-volatile memory array using the first offset program verify level; and
program a second set of the memory cells of the non-volatile memory array using the second offset program verify level;
wherein the first and second offset program verify levels are determined to provide more even distribution of programming levels, thereby reducing an overall bit error rate associated with the non-volatile memory array.
2. The data storage device of claim 1 , wherein the controller is further configured to program one or more of the memory cells using multi-level cell (MLC) programming.
3. The data storage device of claim 1 , wherein said determining the first offset program verify level is based at least in part on a program/erase (P/E) count associated with the first set of memory cells.
4. The data storage device of claim 1 , wherein said determining the first offset program verify level is based at least in part on a bit error rate associated with the first set of memory cells.
5. The data storage device of claim 1 , wherein the first offset program verify level is determined by a real-time calculation based at least in part on the temperature.
6. A data storage device comprising:
a non-volatile memory array including a plurality of non-volatile memory cells; and
a controller configured to:
receive a signal indicating a temperature of at least a portion of the data storage device;
determine a first offset program verify level associated with a first programming level based at least in part on the temperature, said determining comprising adding an offset value to a default program verify level, the offset value being based at least in part on the temperature; and
program a first set of the memory cells of the non-volatile memory array using the first offset program verify level;
wherein the offset value is greater than zero when the temperature is greater than or equal to a first predetermined temperature threshold, and wherein the offset value is less than zero when the temperature is lower than a second predetermined temperature threshold.
7. The data storage device of claim 6 , wherein the first predetermined temperature threshold is approximately 25° C.
8. A data storage device comprising:
a non-volatile memory array including a plurality of non-volatile memory cells; and
a controller configured to:
receive a signal indicating a temperature of at least a portion of the data storage device;
maintain a system table associating temperature values with program verify level offset values;
determine a first offset program verify level associated with a first programming level based at least in part on the temperature and the system table; and
program a first set of the memory cells of the non-volatile memory array using the first offset program verify level.
9. A data storage device comprising:
a non-volatile memory array including a plurality of non-volatile memory cells; and
a controller configured to:
receive a signal indicating a temperature of at least a portion of the data storage device;
determine a first offset program verify level associated with a first programming level based at least in part on the temperature;
program a first set of the memory cells of the non-volatile memory array using the first offset program verify level;
determine an offset voltage read level associated with the first programming level based at least in part on the temperature; and
read a second set of the memory cells of the non-volatile memory array using the offset voltage read level.
10. A method of programming data in a data storage system comprising a non-volatile memory array, the method comprising:
receiving a signal indicating a temperature of at least a portion of a data storage device;
determining a first offset program verify level associated with a first programming level based at least in part on the temperature;
programming a first set of memory cells of a non-volatile memory array of the data storage device using the first offset program verify level;
determining an offset voltage read level associated with the first programming level based at least in part on the temperature; and
reading a second set of the memory cells of the non-volatile memory array using the offset voltage read level;
wherein the method is performed under the control of a controller of the data storage device.
11. The method of claim 10 , further comprising:
determining a second offset program verify level associated with a second programming level based at least in part on the temperature; and
programming a third set of the memory cells of the non-volatile memory array using the second offset program verify level.
12. The method of claim 10 , wherein said determining the first offset program verify level is based at least in part on a program/erase (P/E) count associated with the first set of memory cells.
13. The method of claim 10 , wherein said determining the first offset program verify level is based at least in part on a bit error rate associated with the first set of memory cells.
14. The method of claim 10 , wherein said determining the first offset program verify level comprises adding an offset value to a default program verify level, the offset value being based at least in part on the temperature.
15. The method of claim 10 , further comprising maintaining a system table associating temperature values with program verify level offset values.
16. The method of claim 15 , wherein said determining the first offset program verify level comprises referencing the system table.