IP Library Granted Patent US 10,509,598
Granted Patent B2
US 10,509,598 · App. 15/897,923 · Granted Dec 17, 2019

Method and apparatus for programming flash based storage using segmented writes

Inventors: Navneeth Kankani (Fremont, CA); Sarath Chandran Puthen Thermadam (San Jose, CA); Namasivayam Raghunathan (San Jose, CA)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F3/0659G06F3/0604G06F3/0679G11C16/10G11C16/26G11C16/0483
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Quick Facts
Patent No.
US 10,509,598
App. No.
15/897,923
Granted
Dec 17, 2019
Kind
B2
Abstract

Systems and methods are disclosed for writing data to a non-volatile memory (NVM) using a segmented write process. The NVM uses a plurality of program loops to write data to the NVM. The NVM groups the plurality of program loops into a plurality of write segments, and each write segment includes a distinct set of the plurality of program loops. The write segments are separated by a dwell time that allows read access before the data is written to the NVM.

Claims (88)

1. A method of operating a non-volatile memory (NVM), the method comprising:

receiving a write command comprising first data;

determining characteristics for a plurality of program loops used to write the first data to the NVM;

grouping the plurality of program loops into a plurality of write segments, each write segment comprising a distinct set of the plurality of program loops;

determining a dwell time between adjacent write segments; and

writing the first data to the NVM by performing the plurality of write segments that are separated in time by the dwell time.

2. The method of claim 1 , further comprising:

reading second data from the NVM during the dwell time between adjacent write segments before completing all the write segments.

3. The method of claim 2 ,

wherein the writing comprises writing the first data to a first flash die of the NVM via a data channel among a plurality of data channels, and

wherein the reading comprises reading the second data from a second flash die of the NVM via the same data channel during the dwell time.

4. The method of claim 2 , further comprising:

receiving a first command for writing the first data to the NVM; and

receiving a second command for reading the second data from the NVM,

wherein the second command is received after the first command.

5. The method of claim 4 , wherein the first command is received prior to writing the first data to the NVM, and the second command is received prior to completing the plurality of write segments.

6. The method of claim 1 , wherein determining the dwell time comprises determining the dwell time based on a write bandwidth requirement of the NVM.

7. The method of claim 1 ,

wherein the adjacent write segments comprise a first write segment and a second write segment, and

wherein a starting program voltage of the second write segment is based on an ending program voltage of the first write segment.

8. The method of claim 1 , wherein the writing comprises:

determining a program loop count for a current write segment;

if the program loop count is smaller than a maximum loop count of the current write segment, continuing writing the first data to the NVM; and

if the program loop count is not smaller than the maximum loop count of the current write segment, ending the writing of the current write segment.

9. The method of claim 1 , wherein the writing comprises:

performing a first write segment of the plurality of write segments to write the first data to the NVM;

waiting for the dwell time; and

performing a second write segment of the plurality of write segments to write the first data to the NVM after waiting for the dwell time.

10. A solid state device (SSD) comprising:

a non-volatile memory (NVM), and

a controller operatively coupled to the NVM;

wherein the controller is configured to:

receive a write command comprising first data;

determine characteristics for a plurality of program loops used to write the first data to the NVM;

group the plurality of program loops into a plurality of write segments, each write segment comprising a distinct set of the program loops;

determine a dwell time between adjacent write segments; and

write the first data to the NVM by performing the plurality of write segments that are separated by the dwell time.

11. The SSD of claim 10 , wherein the controller is further configured to:

read second data from the NVM during the dwell time between adjacent write segments before completing all the write segments.

12. The SSD of claim 11 , wherein the controller is further configured to:

write the first data to a first flash die of the NVM via a data channel among a plurality of data channels; and

read the second data from a second flash die of the NVM via the same data channel during the dwell time.

13. The SSD of claim 11 , wherein the controller is further configured to:

receive a first command including the write command for writing the first data to the NVM; and

receive a second command for reading the second data from the NVM, wherein the second command is received after the first command.

14. The SSD of claim 13 , wherein the controller is further configured to:

receive the first command prior to writing the first data to the NVM; and

receive the second command prior to completing the plurality of write segments.

15. The SSD of claim 10 , wherein the controller is further configured to:

determine the dwell time based on a write bandwidth requirement of the NVM.

16. The SSD of claim 10 ,

wherein the adjacent write segments comprise a first write segment and a second write segment, and

wherein a starting program voltage of the second write segment is based on an ending program voltage of the first write segment.

17. The SSD of claim 10 , wherein the controller is further configured to write the first data to the NVM by:

determining a program loop count for a current write segment;

if the program loop count is smaller than a maximum loop count of the current write segment, continuing writing the first data to the NVM; and

if the program loop count is not smaller than the maximum loop count of the current write segment, ending the writing of the current write segment.

18. The SSD of claim 10 , wherein the controller is further configured to write the first data to the NVM by:

performing a first write segment of the plurality of write segments to write the first data to the NVM;

waiting for the dwell time; and

performing a second write segment of the plurality of write segments to write the first data to the NVM after waiting for the dwell time.

19. A non-volatile memory (NVM) comprising:

means for receiving a write command comprising first data;

means for determining characteristics for a plurality of program loops used to write the first data to the NVM;

means for grouping the plurality of program loops into a plurality of write segments, each write segment comprising a distinct set of the plurality of program loops;

means for determining a dwell time between adjacent write segments; and

means for writing the first data to the NVM by performing the plurality of write segments that are separated in time by the dwell time.

20. The NVM of claim 19 , further comprising:

means for reading second data from the NVM during the dwell time between adjacent write segments before completing all the write segments.

21. The NVM of claim 20 ,

wherein the means for writing is configured to write the first data to a first flash die of the NVM via a data channel among a plurality of data channels, and

wherein the means for reading is configured to read the second data from a second flash die of the NVM via the same data channel during the dwell time.

22. The NVM of claim 20 , further comprising:

means for receiving a first command including the write command for writing the first data to the NVM; and

means for receiving a second command for reading the second data from the NVM, wherein the second command is received after the first command.

23. The NVM of claim 22 , wherein the first command is received prior to writing the first data to the NVM, and the second command is received prior to completing the plurality of write segments.

24. The NVM of claim 19 , wherein the means for determining the dwell time is configured to determine the dwell time based on a write bandwidth requirement of the NVM.

25. The NVM of claim 19 ,

wherein the adjacent write segments comprise a first write segment and a second write segment, and

wherein a starting program voltage of the second write segment is based on an ending program voltage of the first write segment.

26. The NVM of claim 19 , wherein the means for writing is configured to:

determine a program loop count for a current write segment;

if the program loop count is smaller than a maximum loop count of the current write segment, continue writing the first data to the NVM; and

if the program loop count is not smaller than the maximum loop count of the current write segment, end the writing of the current write segment.

27. The NVM of claim 19 , wherein the means for writing is configured to:

perform a first write segment of the plurality of write segments to write the first data to the NVM;

wait for the dwell time; and

perform a second write segment of the plurality of write segments to write the first data to the NVM after waiting for the dwell time.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2018
From: KANKANI, NAVNEETH; PUTHEN THERMADAM, SARATH CHANDRAN; RAGHUNATHAN, NAMASIVAYAM
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 044953/0699 →