Storage system and method for data recovery after detection of an uncorrectable error
A storage system caches, in volatile memory, data read from non-volatile memory. After detecting an uncorrectable error in the data cached in the volatile memory, the storage system replaces the cached data with data re-read from the non-volatile memory and updated to reflect any changes made to the data after it was stored in the non-volatile memory. The storage system can also analyze a pattern in data adjacent to the uncorrectable error and predict corrected data based on the pattern.
1. A storage system comprising:
a non-volatile memory; and
a controller coupled to the non-volatile memory and configured to:
read logical-to-physical address mapping data from the non-volatile memory, wherein the logical-to-physical address mapping data comprises an existing entry that translates a logical address to a physical address;
write the logical-to-physical address mapping data read from the non-volatile memory in a first volatile memory;
receive a write command to write data to the logical address;
generate a new entry for the logical-to-physical address mapping data that translates the logical address to a new physical address;
write the new entry in a second volatile memory;
update the logical-to-physical address mapping data written in the first volatile memory by reading the new entry from the second volatile memory and replacing the existing entry in the logical-to-physical address mapping data written in the first volatile memory with the new entry;
determine whether an uncorrectable error exists in the updated logical-to-physical address mapping data written in the first volatile memory; and
in response to determining that the uncorrectable error exists in the updated logical-to-physical address mapping data written in the first volatile memory:
recreate the updated logical-to-physical address mapping data in the first volatile memory by:
reading the logical-to-physical address mapping data from the non-volatile memory;
reading the new entry from the second volatile memory; and
merging the new entry into the logical-to-physical address mapping data read from the non-volatile memory; and
store the recreated logical-to-physical address mapping data in the first volatile memory.
2. The storage system of claim 1 , wherein the controller is further configured to determine whether there is a flush in progress for consolidation.
3. The storage system of claim 1 , wherein the controller is further configured to perform the following in response to determining that a control block was updated after a last consolidation:
re-load data from the control block;
scan written pages in open blocks in the non-volatile memory;
rebuild the data in the second volatile memory; and
merge the rebuilt data into the first volatile memory.
4. The storage system of claim 1 , wherein the first and second volatile memories are both in the storage system.
5. The storage system of claim 1 , wherein the first volatile memory is in a host memory buffer and the second volatile memory is in the storage system.
6. The storage system of claim 1 , wherein the first volatile memory comprises dynamic random access memory and the second volatile memory comprises static random access memory.
7. The storage system of claim 1 , wherein the non-volatile memory comprises a three-dimensional memory.
8. The storage system of claim 1 , wherein the controller is further configured to:
analyze a pattern in data adjacent to the uncorrectable error;
predict corrected data based on the pattern; and
store the predicted corrected data in the first volatile memory.
9. The storage system of claim 8 , wherein the pattern comprises a general linear pattern.
10. The storage system of claim 8 , wherein the pattern comprises an initial pattern.
11. The storage system of claim 8 , wherein the pattern comprises a multi-linear pattern.
12. In a storage system comprising a non-volatile memory, a method comprising:
reading logical-to-physical address mapping data from the non-volatile memory, wherein the logical-to-physical address mapping data comprises an existing entry that translates a logical address to a physical address;
writing the logical-to-physical address mapping data read from the non-volatile memory in a first volatile memory;
receiving a write command to write data to the logical address;
generating a new entry for the logical-to-physical address mapping data that translates the logical address to a new physical address;
writing the new entry in a second volatile memory;
updating the logical-to-physical address mapping data written in the first volatile memory by reading the new entry from the second volatile memory and replacing the existing entry in the logical-to-physical address mapping data written in the first volatile memory with the new entry;
determining whether an uncorrectable error exists in the updated logical-to-physical address mapping data written in the first volatile memory; and
in response to determining that the uncorrectable error exists in the updated logical-to-physical address mapping data written in the first volatile memory:
recreating the updated logical-to-physical address mapping data in the first volatile memory by:
reading the logical-to-physical address mapping data from the non-volatile memory;
reading the new entry from the second volatile memory; and
merging the new entry into the logical-to-physical address mapping data read from the non-volatile memory; and
storing the recreated logical-to-physical address mapping data in the first volatile memory.
13. The method of claim 12 , further comprising:
analyzing a pattern in data adjacent to the uncorrectable error;
predicting corrected data based on the pattern; and
storing the predicted corrected data in the first volatile memory.
14. The method of claim 13 , wherein the pattern comprises a general linear pattern.
15. The method of claim 13 , wherein the pattern comprises an initial pattern.
16. The method of claim 13 , wherein the pattern comprises a multi-linear pattern.
17. The method of claim 12 , wherein the volatile memory is in the storage system.
18. The method of claim 12 , wherein the volatile memory is in a host memory buffer.
19. The method of claim 12 , wherein the volatile memory comprises dynamic random access memory.
20. A storage system comprising:
a non-volatile memory;
means for reading logical-to-physical address mapping data from the non-volatile memory, wherein the logical-to-physical address mapping data comprises an existing entry that translates a logical address to a physical address;
means for writing the logical-to-physical address mapping data read from the non-volatile memory in a first volatile memory;
means for receiving a write command to write data to the logical address;
means for generating a new entry for the logical-to-physical address mapping data that translates the logical address to a new physical address;
means for writing the new entry in a second volatile memory;
means for updating the logical-to-physical address mapping data written in the first volatile memory by reading the new entry from the second volatile memory and replacing the existing entry in the logical-to-physical address mapping data written in the first volatile memory with the new entry;
means for determining whether an uncorrectable error exists in the updated logical-to physical address mapping data written in the first volatile memory; and
means for, in response to determining that the uncorrectable error exists in the updated logical-to-physical address mapping data written in the first volatile memory:
recreating the updated logical-to-physical address mapping data in the first volatile memory by:
reading the logical-to-physical address mapping data from the non-volatile memory;
reading the new entry from the second volatile memory; and
merging the new entry into the logical-to-physical address mapping data read from the non-volatile memory; and
storing the recreated logical-to-physical address mapping data in the first volatile memory.