IP Library Granted Patent US 11,853,564
Granted Patent B1
US 11,853,564 · App. 17/843,675 · Granted Dec 26, 2023

Key value data storage device with improved utilization for short key value pairs

Inventors: David Avraham (Even Yehuda, IL); Alexander Bazarsky (Holon, IL); Ran Zamir (Ramat Gan, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/0622G06F3/0655G06F3/0679
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Quick Facts
Patent No.
US 11,853,564
App. No.
17/843,675
Granted
Dec 26, 2023
Kind
B1
Abstract

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive key value (KV) pair data from a host device, where the KV pair data includes a key and a value, store the received KV pair data in an intermediate storage location, match the received KV pair data to another one or more KV pair data stored in the intermediate storage location, where the matching is based on a utilization parameter of a storage container of the memory device, aggregate the matched received KV pair data and the another one or more KV pair data stored in the intermediate storage location, and program the aggregated KV pair data to the memory device.

Claims (42)

1. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to:

receive key value (KV) pair data from a host device, wherein the KV pair data includes a key and a value;

store the received KV pair data in an intermediate storage location;

match the received KV pair data to another one or more KV pair data stored in the intermediate storage location, wherein the matching is based on a utilization parameter of a storage container of the memory device;

aggregate the matched received KV pair data and the another one or more KV pair data stored in the intermediate storage location; and

program the aggregated KV pair data to the memory device.

2. The data storage device of claim 1 , wherein the intermediate storage location is random access memory.

3. The data storage device of claim 1 , wherein the intermediate storage location is single level cell (SLC) memory or hybrid block memory.

4. The data storage device of claim 1 , wherein the utilization parameter is a minimum percentage of data to be stored in the storage container of the memory device.

5. The data storage device of claim 4 , wherein the aggregating is to at least the minimum percentage.

6. The data storage device of claim 4 , wherein the minimum percentage usage is between about 90% and about 100%.

7. The data storage device of claim 4 , wherein the minimum percentage usage is adjusted based on a fullness of the intermediate storage location, wherein the minimum percentage usage is decreased when the fullness of the intermediate storage location increases, and wherein the minimum percentage usage is increased when the fullness of the intermediate storage location decreases.

8. The data storage device of claim 1 , wherein the matching comprises grouping KV pair data of a first KV format with KV pair data of a second KV format.

9. The data storage device of claim 8 , wherein the matching further comprises analyzing a plurality of KV formats in the data storage device, and wherein the analyzing occurs when a KV format is added to the plurality of KV formats or removed from the plurality of KV formats.

10. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to:

analyze a plurality of key value (KV) formats present in the data storage device;

generate a grouping of two or more KV formats based on the analyzing, wherein the generating associates a first KV format with one or more second KV formats, and wherein the generated grouping is based on reaching at least a utilization parameter of a storage container of the memory device based on the grouping; and

store the generated grouping for use by the controller to group two or more KV pair data received from a host device.

11. The data storage device of claim 10 , wherein each KV format is defined by the host device.

12. The data storage device of claim 11 , wherein a KV format is a length of a value of a KV pair data.

13. The data storage device of claim 10 , wherein generating the grouping is based on a tradeoff between the utilization parameter of the storage container and a complexity of a KV format.

14. The data storage device of claim 10 , wherein the controller is further configured to:

maintain a list of generated groupings, wherein the list of generated groupings includes at least a first generated grouping and a second generated grouping;

sort the list of generated groupings, wherein the first generated grouping is a first listing and the second generated grouping is a second listing in the list of generated groupings; and

program KV pair data associated with a first generated grouping of the sorted list of generated groupings to the memory device.

15. The data storage device of claim 14 , wherein the programming is in response to a threshold capacity of the memory device storing a plurality of KV pair data being reached.

16. The data storage device of claim 14 , wherein the sorting is based on the utilization parameter, wherein the KV pair data associated with the first generated grouping is programmed prior to programming KV pair data associated with the second generated grouping, and wherein the utilization parameter of the first generated grouping is greater than the utilization parameter of the second generated grouping.

17. The data storage device of claim 14 , wherein the sorting is based on a number of group members of each of the generated groupings, wherein the KV pair data associated with the first generated grouping is programmed prior to programming KV pair data associated with the second generated grouping, and wherein the number of group members of the first generated grouping is greater than the number of group members of the second generated grouping.

18. The data storage device of claim 14 , wherein the controller is further configured to:

store the KV pair data associated with the first generated grouping in single level cell (SLC) memory prior to programming the KV pair data to the memory device; and

store KV pair data associated with the second generated grouping in volatile memory.

19. A data storage device, comprising:

memory means; and

a controller coupled to the memory means, wherein the controller is configured to:

store received key value (KV) pair data in a first location of the memory means;

aggregate a first KV pair data associated with a first KV format with a second KV pair data associated with a second KV format, wherein the first KV format and the second KV format are distinct, and wherein the aggregating is to at least a utilization parameter of a second location of the memory means; and

program the aggregated KV pair data to the second location of the memory means when the utilization parameter of the second location is reached or exceeded.

20. The data storage device of claim 19 , wherein the first location and the second location are distinct.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2022
From: AVRAHAM, DAVID; BAZARSKY, ALEXANDER; ZAMIR, RAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 060246/0241 →