IP Library Granted Patent US 11,675,512
Granted Patent B2
US 11,675,512 · App. 17/878,253 · Granted Jun 13, 2023

Storage system and method for using read and write buffers in a memory

Inventors: Rotem Sela (Haifa, IL); Einav Zilberstein (Had Hasharon, IL); Karin Inbar (Kfar Saba, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/064G06F3/0604G06F3/0673G06F12/0888G06F12/1009G06F2212/657G11C11/5621G11C11/5671
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Quick Facts
Patent No.
US 11,675,512
App. No.
17/878,253
Granted
Jun 13, 2023
Kind
B2
Abstract

A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.

Claims (40)

1. In a storage system comprising a memory, wherein the memory comprises a first set of blocks allocated as a write buffer and a second set of blocks, wherein the first set of blocks has a lower latency than the second set of blocks, a method comprising:

receiving, from a host, data to be stored in the memory;

storing the data in the write buffer;

receiving, from the host, a command to flush the write buffer to the second set of blocks in the memory;

determining whether the data is to be retained in the write buffer despite the command to flush the write buffer; and

in response to determining that the data is to be retained in the write buffer, retaining the data in the write buffer despite the command to flush the write buffer.

2. The method of claim 1 , further comprising:

receiving, from the host, a command to flush the data retained in the write buffer.

3. The method of claim 1 , further comprising:

receiving, from the host, information indicating that the data is to be retained in the write buffer.

4. The method of claim 3 , wherein the information indicates one of a plurality of different retention levels.

5. The method of claim 3 , wherein the information comprises a dedicated command.

6. The method of claim 1 , further comprising:

receiving, from the host, a maximum size of the write buffer.

7. The method of claim 1 , wherein the first set of blocks comprises single-level cell (SLC) blocks and the second set of blocks comprises multi-level cell (MLC) blocks.

8. The method of claim 1 , wherein the first set of blocks comprises XPOINT memory and the second set of blocks comprises flash memory.

9. The method of claim 1 , wherein the memory comprises a three-dimensional memory.

10. A storage system comprising:

a memory comprising a first set of blocks allocated as a write buffer and a second set of blocks, wherein the first set of blocks has a lower latency than the second set of blocks; and

a controller configured to:

store the data in the write buffer;

receive, from the host, a command to flush the write buffer to the second set of blocks in the memory;

determine whether the data is to be retained in the write buffer despite the command to flush the write buffer; and

in response to determining that the data is to be retained in the write buffer, retain the data in the write buffer despite the command to flush the write buffer.

11. The storage system of claim 10 , wherein the controller is further configured to receive, from the host, a command to flush the data retained in the write buffer.

12. The storage system of claim 10 , wherein the controller is further configured to receive, from the host, information indicating that the data is to be retained in the write buffer.

13. The storage system of claim 12 , wherein the information indicates one of a plurality of different retention levels.

14. The storage system of claim 12 , wherein the information comprises a dedicated command.

15. The storage system of claim 10 , wherein the controller is further configured to receive, from the host, a maximum size of the write buffer.

16. The storage system of claim 10 , wherein the first set of blocks comprises single-level cell (SLC) blocks and the second set of blocks comprises multi-level cell (MLC) blocks.

17. The storage system of claim 10 , wherein the first set of blocks comprises XPOINT memory.

18. The storage system of claim 17 , wherein the second set of blocks comprises flash memory.

19. The storage system of claim 10 , wherein the memory comprises a three-dimensional memory.

20. A storage system comprising:

a memory comprising a first set of blocks allocated as a write buffer and a second set of blocks, wherein the first set of blocks has a lower latency than the second set of blocks;

means for receiving, from a host, data to be stored in the memory;

means for storing the data in the write buffer;

means for receiving, from the host, a command to flush the write buffer to the second set of blocks in the memory;

means for determining whether the data is to be retained in the write buffer despite the command to flush the write buffer; and

means for retaining the data in the write buffer despite the command to flush the write buffer in response to determining that the data is to be retained in the write buffer.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2022
From: SELA, ROTEM; ZILBERSTEIN, EINAV; INBAR, KARIN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 060685/0312 →