IP Library Granted Patent US 11,537,320
Granted Patent B2
US 11,537,320 · App. 16/780,216 · Granted Dec 27, 2022

Storage system and method for host memory access

Inventors: Rotem Sela (Haifa, IL); Amir Shaharabany (Kochav Yair, IL); Eliad Adi Klein (Sunnyvale, CA)
Assignee: Western Digital Technologies, Inc.
G06F3/0659G06F12/10G06F1/3296G06F3/0604G06F3/0673G06F21/602G06F2212/657G09G2360/125
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Quick Facts
Patent No.
US 11,537,320
App. No.
16/780,216
Granted
Dec 27, 2022
Kind
B2
Abstract

A storage system and method for host memory access are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive a write command from the host that is recognized by the storage system as a read host memory command; in response to receiving the write command, send an identification of a location in the host memory to the host; and receive, from the host, data that is stored in the location in the host memory. Other embodiments are provided.

Claims (62)

1. A storage system comprising:

a memory; and

a controller configured to communicate with the memory and with a host comprising host memory, wherein the controller is further configured to:

receive a write command from the host, wherein the write command comprises a command name parameter that indicates that the write command and is actually a read host memory command sent by the host to initiate establishment of a read channel between the host memory and the controller;

in response to recognizing the write command as the read host memory command because of the command name parameter, establish the read channel between the host memory and the controller;

receive a read command from the host, wherein the read command comprises a command name parameter that indicates that the read command is actually a write host memory command sent by the host to initiate establishment of a write channel between the host memory and the controller;

in response to recognizing the read command as the write host memory command because of the command name parameter, establish the write channel between the host memory and the controller;

send, to the host via the write channel, at least a part of a logical-to-physical address table stored in the memory for storage in the host memory;

receive a read command from the host comprising a logical block address;

send, to the host via the read channel, an identification of a location in the host memory that stores an entry for the logical block address in the at least a part of the logical-to-physical address table stored in the host memory; and

receive, from the host via the read channel, the entry for the logical block address; wherein:

the write and read channels are kept open until the storage system powers off; and

the host is configured to ignore timeouts to keep the write and read channels open.

2. The storage system of claim 1 , wherein the write command comprises a first parameter that identifies a start address of an area of the host memory designated for use by the storage system and a second parameter that identifies a size of the area.

3. The storage system of claim 1 , wherein the identification of the location in the host memory is sent as pail of a ready-to-transfer response to the write command.

4. The storage system of claim 1 , wherein the identification of the location in the host memory comprises an address offset and payload size.

5. The storage system of claim 1 , wherein:

the write command further comprises a logical block address, and

the controller is further configured to ignore the logical block address.

6. The storage system of claim 1 , wherein the host memory comprises a first area designated for se by the storage system to read and write data, a second area designated for storing data read from the storage system by the host, and a third area designated for storing data to be written to the storage system by the host, the first, second, and third areas being non-overlapping areas.

7. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

8. The storage system of claim 1 , wherein the controller is further configured to receive a request from the host to enter a sleep state while keeping several commands active.

9. The storage system of claim 1 , wherein the controller is further configured to be able to signal the host irrespective of whether a link connecting the host and the storage system is in a low-power mode.

10. The storage system of claim 1 , wherein the host is further configured to enable a storage sleep state.

11. The storage system of claim 1 , wherein the storage system is configured to be integrated in the host.

12. A method comprising:

performing the following in a storage system in communication with a host comprising host memory, wherein the storage system comprises a memory and a controller:

receiving a read command from the host, wherein the read command comprises a command name parameter that indicates that the read command is actually a write host memory command sent by the host to initiate establishment of a write channel between the host memory and the controller;

in response to recognizing the read command as the write host memory command because the command name parameter indicates that the read command is the write host memory command, establishing the write channel between the host memory and the controller;

receiving a read command from the host comprising a logical block address in the memory; and

in response to receiving the read command:

predicting a next logical block address to be read requested by the host; and

sending, to the host via the write channel, data stored in the next logical block address in the memory for storage in the host memory;

wherein:

the write channel is kept open until the storage system powers off; and

the host is configured to ignore timeouts to keep the write channel open.

13. The method of claim 12 , wherein the host is further configured to enable a storage sleep state.

14. The method of claim 12 , further comprising:

receiving a write command from the host, wherein the write command comprises a command name parameter that indicates that the write command is actually a read host memory command sent by the host to initiate establishment of a read channel between the host memory and the controller; and

in response to recognizing the write command as the read host memory command because the command name parameter indicates that the write command is the read host memory command, establishing the read channel between the host memory and the controller.

15. The method of claim 14 , further comprising:

receiving a read command from the host comprising the next logical block address;

reading, via the read channel, the data stored in the host memory; and

sending the data to the host in response to the read command comprising the next logical block address.

16. The method of claim 14 , further comprising:

receiving a write command from the host with a data payload; and

sending, to the host via the write channel, the data payload for storage in the host memory instead of storing the data payload in a volatile memory in the storage system.

17. The method of claim 14 , wherein the read channel is kept open until the storage system powers off.

18. The method of claim 14 , wherein the host is further configured to ignore timeouts to keep the read channel open.

19. A storage system comprising:

a memory;

a controller;

means for receiving a write command from a host comprising host memory, wherein the write command comprises a command name parameter that indicates that the write command is actually a read host memory command sent by the host to initiate establishment of a read channel between the host memory and the controller;

means for establishing Rail the read channel between the host memory and the controller in response to recognizing the write command as the read host memory command because the command name parameter indicates that the write command is the read host memory command;

means for receiving a read command from the host, wherein the read command comprises a command name parameter that indicates that the read command is actually a write host memory command sent by the host to initiate establishment of a write channel between the host memory and the controller;

means for establishing the write channel between the host memory and the controller in response to recognizing the read command as the write host memory command because the command name parameter indicates that the read command is the write host memory command;

means for sending, to the host via the write channel, data stored in a volatile memory in the storage system prior to a sleep or power-down operation;

means for sending, to the host via the read channel after powering up after sleep or power-down, an identification of a location in the host memory that stores the data; and

means for receiving, from the host via the read channel, the data;

wherein:

the write and read channels are kept open until the storage system powers off; and

the host is configured to ignore timeouts to keep the write and read channels open.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 053482 FRAME 0453 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0279 →
SECURITY INTEREST Recorded May 14, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053482/0453 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2020
From: SELA, ROTEM; SHAHARABANY, AMIR; KLEIN, ELIAD ADI
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 051702/0899 →