Granted Patent B2

US 10,949,123 · App. 16/440,233 · Granted Mar 16, 2021

Abstract

Claims (57)

1. A solid state device, comprising:

a controller;

a non-volatile memory comprising a plurality of dies, each die comprising a first plane and a second plane;

a first super-plane-block structured from the first plane of the plurality of dies;

a second super-plane-block structured from the second plane of the plurality of dies; and

a plurality of memory operation instructions that, when executed by the controller, cause the controller to:

receive a first data stream;

write the first data stream to the first super-plane-block;

receive a second data stream;

write the second data stream to the second super-plane-block;

invalidate data of the first super-plane-block; and

erase the first super-plane-block without causing garbage collection of the second super-plane-block.

2. The solid state device of claim 1 , wherein the plurality of memory operation instructions further cause the controller to write a first parity information of the first data stream to a first plane of a XOR die of the first super-plane-block and writing a second parity information of the second data stream to a second plane of the XOR die of the second super-plane-block.

3. The solid state device of claim 1 , wherein the plurality of memory operation instructions further cause the controller to simultaneously write the first data stream to the first super-plane-block and second data stream to the second super-plane-block.

4. The solid state device of claim 1 , wherein the plurality of dies comprises quad-level memory cells.

5. The solid stated device of claim 1 , wherein the first super-plane-block and the second super-plane-block form erasable units.

6. The solid state device of claim 1 , further comprising a logical page cache, wherein the plurality of memory operation instructions further cause the controller to flush the first data stream to the first super-plane block and to flush the second data stream to the second super-plane-block.

7. A solid state device, comprising:

a non-volatile memory comprising a plurality of dies having multiple planes; and

a controller coupled to the non-volatile memory configured to:

structure the non-volatile memory into a plurality of super-plane-blocks, each super-plane-block spanning separate planes of the plurality of dies;

cache a plurality of data streams to a logical page cache;

flush the logical page cache in a size to substantially fill the one or more of the plurality of super-plane-blocks; and

write a plurality of data streams from the logical page cache into the plurality of super-plane-blocks, wherein each data stream of the plurality of data streams is written to one or more separate super-plane-blocks of the plurality of super-plane-blocks.

8. The solid state device of claim 7 , wherein the number of data streams written to the plurality of super-plane-blocks is equal to or less than the number of planes.

9. The solid state device of claim 7 , wherein the logical page cache is selecting from a host cache, a SSD SRAM cache, a SSD DRAM cache, a SSD NAND flash cache, and combinations thereof.

10. The solid state device of claim 7 , wherein the non-volatile memory comprises a plurality of user data dies and a XOR die, wherein the controller is further configured to:

write a parity information of a first data stream on a first plane of the XOR die; and

write a parity information of a second data stream on a second plane of the XOR die.

11. The solid state device of claim 10 , wherein the controller is further configured to:

structure the non-volatile memory into a first super-plane-block and a second super-plane-block, the first super-plane-block spanning across a first plane of each user data dies and the second super-plane-block spanning across a second plane of each user data dies;

write the first data stream to the first super-plane-block; and

write the second data stream to the second super-plane-block.

12. The solid state device of claim 11 , wherein the first data stream and the second data stream are interleaved on the plurality of user data dies and wherein the parity information of the first data stream and the parity information of the first data stream are interleaved on first plane and the second plane of the XOR die.

13. A solid state device, comprising:

a non-volatile memory comprising a plurality of user data dies having multiple planes and a XOR die having multiple planes; and

a controller coupled to the non-volatile memory configured to:

structure the non-volatile memory into a first super-plane-block and a second super-plane-block, the first super-plane-block spanning across a first plane of the multiple planes of each of the user data dies and across a first plane of the multiples planes of the XOR die, the second super-plane-block spanning across a second plane of the multiple planes of each of the user data dies and across a second plane of the multiples planes of the XOR die;

write a first data stream to the first super-plane-block;

write a second data stream to the second super-plane-block;

write a parity information of the first data stream on the first plane of the multiple planes of the XOR die;

write a parity information of the second data stream on the second plane of the multiple planes of the XOR die;

invalidate the parity information of the first data stream written to the first super-plane-block; and

erase the parity information of the first data stream without causing garbage collection of the parity information of the second data stream.

14. A solid state device, comprising:

a controller;

a data stream support means for simultaneously writing separate data from two separate data streams on NAND flash memory; and

a plurality of memory operation instructions that, when executed by the controller, cause the controller to simultaneous write separate data to the data stream support means wherein invalidation of the separate data of one of the two separate data streams causes erasure of the separate data of the one of the two separate data streams without garbage collection of the separate data of another of the two separate data streams.

15. The solid state device of claim 14 , wherein the separate data is user data from the two separate data streams.

16. The solid state device of claim 14 , wherein the separate data is parity information from the two separate data streams.

17. A solid state device, comprising:

a non-volatile memory comprising a plurality of dies, each die having a first plane and a second plane; and

a controller comprising a plurality of memory operation instructions that, when executed by the controller, cause the controller to:

structure the non-volatile memory into a first super-device comprising a first super-plane-block spanning the first planes of the dies and a second super-plane-block spanning the second planes of the dies;

write a first data stream into the first super-plane-block spanning the first planes of the first super-device and writing a second data stream into the second super-plane-block spanning the second planes of the first super-device;

structure the non-volatile memory into a second super-device comprising a first super-plane-block spanning the second planes of the dies and a second super-plane-block spanning the first planes of the dies; and

writing the first data stream into the first super-plane-block spanning the second planes of the second super-device and writing the second data stream into the second super-plane-block spanning the first planes of the second super-device.

Assignments (10)