IP Library Granted Patent US 11,221,802
Granted Patent B2
US 11,221,802 · App. 16/897,499 · Granted Jan 11, 2022

Zone allocation for data storage device based on zone reset behavior

Inventors: Phil Reusswig (Santa Clara, CA); Yosief Ataklti (Fremont, CA)
Assignee: Western Digital Technologies, Inc.
G06F3/0679G06F3/064G06F3/0607G06F12/0246G06F12/0891
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Quick Facts
Patent No.
US 11,221,802
App. No.
16/897,499
Granted
Jan 11, 2022
Kind
B2
Abstract

A memory controller includes, in one implementation, a host interface, a memory interface, and a flash translation layer (FTL). The FTL is configured to receive a request from a host device to store data in a zone of a solid-state memory. The FTL is also configured to determine a zone reset rate classification as one of a hot classification, a cold classification, and a normal classification. The FTL is further configured to allocate the zone to a memory die with the fewest free die blocks when the zone reset rate classification is the hot classification. The FTL is also configured to allocate the zone to a memory die with the most free die blocks when the zone reset rate classification is the cold classification. The FTL is further configured to send the data to the memory die for storage therein.

Claims (62)

1. A memory controller, comprising:

a host interface configured to interface with a host device;

a memory interface configured to interface with a solid-state memory; and

a flash translation layer coupled to the host interface and the memory interface, wherein the flash translation layer is configured to:

receive a request from the host device by way of the host interface to store data in a zone of the memory,

determine a zone reset rate classification for the zone as one of a hot classification, a cold classification, and a normal classification, the zone reset rate classification indicating an invalidation rate of the data stored in the zone,

allocate the zone to a die in the memory based on the zone reset rate classification, wherein the zone is allocated to the die with fewest free die blocks when the zone reset rate classification is the hot classification, and wherein the zone is allocated to the die with most free die blocks when the zone reset rate classification is the cold classification, and

send the data to the die in the memory by way of the memory interface for storage in the memory.

2. The memory controller of claim 1 , wherein, to determine the zone reset rate classification, the flash translation layer is further configured to:

increment a zone reset counter each time the zone is reset,

classify the zone with the hot classification when the zone reset counter is greater than a hot threshold,

classify the zone with the cold classification when the zone reset counter is less than a cold threshold, and

classify the zone with the normal classification when the zone reset counter is between the hot threshold and the cold threshold.

3. The memory controller of claim 2 , wherein the flash translation layer is further configured to determine the hot threshold and the cold threshold based on a total number of zone resets for the memory.

4. The memory controller of claim 1 , wherein, to determine the zone reset rate classification, the flash translation layer is further configured to:

increment a zone reset counter each time the zone is reset,

scale the zone reset counter based on a total number of zone resets for the memory to generate a scaled zone reset counter,

classify the zone with the hot classification when the scaled zone reset counter is greater than a hot threshold,

classify the zone with the cold classification when the scaled zone reset counter is less than a cold threshold, and

classify the zone with the normal classification when the scaled zone reset counter is between the hot threshold and the cold threshold.

5. The memory controller of claim 1 , wherein, to determine the zone reset rate classification, the flash translation layer is further configured to determine the zone reset rate classification based on an indication received from the host device.

6. The memory controller of claim 5 , wherein the flash translation layer receives the indication from the host device when the zone is opened.

7. The memory controller of claim 6 , wherein the zone is allocated to any die in the memory with free die blocks when the zone reset rate classification is the normal classification.

8. A method, comprising:

receiving a request from a host device to store data in a zone of a solid-state memory;

determining, with a flash translation layer, a zone reset rate classification for the zone as one of a hot classification, a cold classification, and a normal classification;

allocating, with the flash translation layer, the zone to a die in the memory based on the zone reset rate classification, wherein the zone is allocated to the die with fewest free die blocks when the zone reset rate classification is the hot classification, the zone reset rate classification indicating an invalidation rate of the data stored in the zone, and wherein the zone is allocated to the die with most free die blocks when the zone reset rate classification is the cold classification; and

sending the data to the die in the memory for storage therein.

9. The method of claim 8 , wherein determining the zone reset rate classification further includes:

incrementing a zone reset counter each time the zone is reset,

classifying the zone with the hot classification when the zone reset counter is greater than a hot threshold,

classifying the zone with the cold classification when the zone reset counter is less than a cold threshold, and

classifying the zone with the normal classification when the zone reset counter is between the hot threshold and the cold threshold.

10. The method of claim 9 , further comprising determining, with the flash translation layer, the hot threshold and the cold threshold based on a total number of zone resets for the memory.

11. The method of claim 8 , wherein determining the zone reset rate classification further includes:

incrementing a zone reset counter each time the zone is reset,

scaling the zone reset counter based on a total number of zone resets for the memory to generate a scaled zone reset counter,

classifying the zone with the hot classification when the scaled zone reset counter is greater than a hot threshold,

classifying the zone with the cold classification when the scaled zone reset counter is less than a cold threshold, and

classifying the zone with the normal classification when the scaled zone reset counter is between the hot threshold and the cold threshold.

12. The method of claim 8 , wherein determining the zone reset rate classification further includes determining the zone reset rate classification based on an indication received from the host device.

13. The method of claim 12 , wherein the indication is received from the host device when the zone is opened.

14. The method of claim 8 , wherein the zone is allocated to any die in the memory with free die blocks when the zone reset rate classification is the normal classification.

15. An apparatus, comprising:

means for receiving a request from a host device to store data in a zone of a solid-state memory;

means for determining a zone reset rate classification for the zone as one of a hot classification, a cold classification, and a normal classification the zone reset rate classification indicating an invalidation rate of the data stored in the zone;

means for allocating the zone to a die in the memory based on the zone reset rate classification, wherein the zone is allocated to the die with fewest free die blocks when the zone reset rate classification is the hot classification, and wherein the zone is allocated to the die with most free die blocks when the zone reset rate classification is the cold classification; and

means for sending the data to the die in the memory for storage therein.

16. The apparatus of claim 15 , wherein the means for determining the zone reset rate classification is further configured to:

increment a zone reset counter each time the zone is reset,

classify the zone with the hot classification when the zone reset counter is greater than a hot threshold,

classify the zone with the cold classification when the zone reset counter is less than a cold threshold, and

classify the zone with the normal classification when the zone reset counter is between the hot threshold and the cold threshold.

17. The apparatus of claim 16 , further comprising means for determining the hot threshold and the cold threshold based on a total number of zone resets for the memory.

18. The apparatus of claim 15 , wherein the means for determining the zone reset rate classification is further configured to:

increment a zone reset counter each time the zone is reset,

scale the zone reset counter based on a total number of zone resets for the memory to generate a scaled zone reset counter,

classify the zone with the hot classification when the scaled zone reset counter is greater than a hot threshold,

classify the zone with the cold classification when the scaled zone reset counter is less than a cold threshold, and

classify the zone with the normal classification when the scaled zone reset counter is between the hot threshold and the cold threshold.

19. The apparatus of claim 15 , wherein the means for determining the zone reset rate classification is further configured to determine the zone reset rate classification based on an indication received from the host device.

20. The apparatus of claim 15 , wherein the means for allocating the zone is further configured to allocate the zone to any die in the memory with free die blocks when the zone reset rate classification is the normal classification.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2020
From: REUSSWIG, PHIL; ATAKLTI, YOSIEF
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 053110/0455 →