IP Library Granted Patent US 11,251,812
Granted Patent B2
US 11,251,812 · App. 16/909,815 · Granted Feb 15, 2022

Encoding and decoding of hamming distance-based binary representations of numbers

Inventor: Minghai Qin (San Jose, CA)
Assignee: Western Digital Technologies, Inc.
H03M13/19G06F11/1044G11C29/52H03M7/24H03M13/05H03M13/255G11C13/0004G11C2029/0411
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Quick Facts
Patent No.
US 11,251,812
App. No.
16/909,815
Granted
Feb 15, 2022
Kind
B2
Abstract

Systems and methods for dynamically encoding and decoding binary numbers using linear-time algorithms that encode and decode Hamming Distance-Based representations for the binary numbers are described. The binary numbers may correspond with integer values, such as 64-bit, 128-bit, or 256-bit integer values. In some cases, in response to detecting that a binary number is to be stored using a particular type of memory (e.g., a phase change memory), the binary number may first be encoded using a Hamming Distance-Based representation and then the encoded data may be written to the particular type of memory. The binary number may be encoded by generating a binary string or a binary array representing the binary number such that if one bit flips within the binary string or the binary array, the maximum distortion in the number is less than a threshold amount (e.g., less than 256).

Claims (51)

1. An apparatus, comprising:

a memory buffer; and

one or more control circuits configured to acquire a first set of data associated with a binary number and detect that the first set of data is to be stored using a particular type of semiconductor memory, the first set of data comprises a total number of bits, the one or more control circuits configured to store the first set of data associated with the binary number in the memory buffer and generate a Hamming distance-based encoding for the first set of data associated with the binary number in response to detection that the first set of data is to be stored using the particular type of semiconductor memory, the one or more control circuits configured to encode the first set of data associated with the binary number using the Hamming distance-based encoding, the one or more control circuits configured to detect that the binary number minus the total number of bits choose one is greater than or equal to zero and reduce the binary number by the total number of bits choose one in response to detection that the binary number minus the total number of bits choose one is greater than or equal to zero, the one or more control circuits configured to initialize a loop variable and an output array, the one or more control circuits configured to determine a Hamming weight for the first set of data, the one or more control circuits configured to detect that the reduced binary number is greater than or equal to the total number of bits minus one choose the Hamming weight for the first set of data and set a bit position within the output array corresponding with the loop variable to one in response to detection that the reduced binary number is greater than or equal to the total number of bits minus one choose the Hamming weight for the first set of data, the one or more control circuits configured to output the output array as the Hamming distance-based encoding for the first set of data, the one or more control circuits configured to store the Hamming distance-based encoding for the first set of data using a semiconductor memory of the particular type of semiconductor memory, wherein the semiconductor memory comprises re-writeable non-volatile memory cells.

2. The apparatus of claim 1 , wherein:

the semiconductor memory comprises a phase change memory.

3. The apparatus of claim 2 , wherein:

the phase change memory includes a chalcogenide material.

4. The apparatus of claim 1 , wherein:

the one or more control circuits configured to detect that the particular type of semiconductor memory comprises a phase change memory and generate the Hamming distance-based encoding for the first set of data in response to detection that the particular type of semiconductor memory comprises the phase change memory.

5. The apparatus of claim 1 , wherein:

the one or more control circuits configured to detect that the semiconductor memory of the particular type of semiconductor memory has experienced more than a threshold number of bit errors and generate the Hamming distance-based encoding for the first set of data in response to detection that the semiconductor memory of the particular type of semiconductor memory has experienced more than the threshold number of bit errors.

6. The apparatus of claim 1 , wherein:

the one or more control circuits configured to detect that the semiconductor memory has a threshold number of defects and generate the Hamming distance-based encoding for the first set of data in response to detection that the semiconductor memory has the threshold number of defects.

7. The apparatus of claim 1 , wherein:

the one or more control circuits configured to detect that the semiconductor memory has at least a threshold number of word line defects and generate the Hamming distance-based encoding for the first set of data in response to detection that the semiconductor memory has at least the threshold number of word line defects.

8. The apparatus of claim 1 , wherein:

the one or more control circuits configured to detect that data previously written to the semiconductor memory has experienced at least a threshold number of bit errors and generate the Hamming distance-based encoding for the first set of data in response to detection that the data previously written to the semiconductor memory has experienced at least the threshold number of bit errors.

9. The apparatus of claim 1 , wherein:

the one or more control circuits are arranged on a first integrated circuit; and

the semiconductor memory is arranged on a second integrated circuit.

10. The apparatus of claim 1 , wherein:

the one or more control circuits are arranged on a first die;

the memory buffer is arranged on the first die; and

the semiconductor memory is arranged on a second die.

11. An apparatus, comprising:

a memory buffer; and

a control circuit configured to acquire a first set of data associated with a binary number and store the first set of data associated with the binary number using the memory buffer, the first set of data comprises a total number of bits, the control circuit configured to encode the first set of data associated with the binary number using a Hamming distance-based encoding, the control circuit configured to determine a Hamming weight for the first set of data and detect that the binary number minus the total number of bits choose one is greater than or equal to zero, the control circuit configured to reduce the binary number by the total number of bits choose one in response to detection that the binary number minus the total number of bits choose one is greater than or equal to zero, the control circuit configured to initialize a loop variable and an output array, the control circuit configured to detect that the reduced binary number is greater than or equal to the total number of bits minus one choose the Hamming weight for the first set of data, the control circuit configured to set a bit position within the output array corresponding with the loop variable to one in response to detection that the reduced binary number is greater than or equal to the total number of bits minus one choose the Hamming weight for the first set of data, the control circuit configured to output the output array as the Hamming distance-based encoding for the first set of data, the control circuit configured to store the Hamming distance-based encoding for the first set of data to be stored using a semiconductor memory, wherein the semiconductor memory comprises re-writeable non-volatile memory cells.

12. The apparatus of claim 11 , wherein:

the control circuit configured to cause the Hamming distance-based encoding for the first set of data to be stored using a phase change memory.

13. The apparatus of claim 12 , wherein:

the control circuit configured to detect that the phase change memory has experienced more than a threshold number of bit errors and cause the Hamming distance-based encoding for the first set of data to be generated in response to detection that the phase change memory has experienced more than the threshold number of bit errors.

14. The apparatus of claim 12 , wherein:

the control circuit configured to detect that the phase change memory has a threshold number of defects and cause the Hamming distance-based encoding for the first set of data to be generated in response to detection that the phase change memory has the threshold number of defects.

15. The apparatus of claim 12 , wherein:

the control circuit configured to detect that the phase change memory has at least a threshold number of word line defects and cause the Hamming distance-based encoding for the first set of data to be generated in response to detection that the phase change memory has at least the threshold number of word line defects.

16. The apparatus of claim 12 , wherein:

the control circuit configured to detect that data previously written to the phase change memory has experienced at least a threshold number of bit errors and cause the Hamming distance-based encoding for the first set of data to be generated in response to detection that the data previously written to the phase change memory has experienced at least the threshold number of bit errors.

17. The apparatus of claim 12 , wherein:

the control circuit is arranged on a first die;

the memory buffer is arranged on the first die; and

the phase change memory is arranged on a second die.

18. A method, comprising:

acquiring a first set of data to be stored using a phase change memory, the first set of data is associated with a binary number;

storing the first set of data associated with the binary number in a memory buffer;

determining a total number of bits for the first set of data and a Hamming weight for the first set of data;

generating a Hamming distance-based encoding for the first set of data associated with the binary number in response to detecting that the first set of data is to be stored using the phase change memory, the generating the Hamming distance-based encoding includes encoding the first set of data associated with the binary number using the Hamming distance-based encoding, the generating the Hamming distance-based encoding for the first set of data includes detecting that the binary number minus the total number of bits choose one is greater than or equal to zero and reducing the binary number by the total number of bits choose one in response to detecting that the binary number minus the total number of bits choose one is greater than or equal to zero, the generating the Hamming distance-based encoding for the first set of data includes detecting that the reduced binary number is greater than or equal to the total number of bits minus one choose the Hamming weight for the first set of data and setting a bit position within an output array to one in response to detecting that the reduced binary number is greater than or equal to the total number of bits minus one choose the Hamming weight for the first set of data, the generating the Hamming distance-based encoding for the first set of data includes outputting the output array as the Hamming distance-based encoding for the first set of data; and

storing the Hamming distance-based encoding for the first set of data using the phase change memory.

19. The method of claim 18 , further comprising:

detecting that the phase change memory has experienced more than a threshold number of bit errors and generating the Hamming distance-based encoding for the first set of data in response to detecting that the phase change memory has experienced more than the threshold number of bit errors.

20. The method of claim 18 , further comprising:

detecting that data previously written to the phase change memory has experienced at least a threshold number of bit errors and generating the Hamming distance-based encoding for the first set of data in response to detecting that the data previously written to the phase change memory has experienced at least the threshold number of bit errors.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2020
From: QIN, MINGHAI
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 053043/0670 →