Physical secure erase of solid state drives
Embodiments of the present disclosure relate to physical secure erase (PSE) of solid state drives (SSDs). One embodiment of a method of PSE of a SSD includes receiving a PSE command, erasing the memory cells of the blocks, programming the memory cells, and programming the select gates to a portion of the blocks. One embodiment of a SSD includes a controller and a plurality of blocks having a plurality of NAND strings. Each NAND string includes connected in series a select gate drain, memory cells, and a select gate source. The SSD includes a memory erasing instruction that cause the controller to erase the memory cells of the block, program the memory cells, and increase the threshold voltage to the select gate drain and/or the select gate source of some of the NAND strings from the blocks.
1. A method of physical secure erase of a solid state drive, the solid state drive comprising a plurality of memory cells for data storage arranged in a plurality of blocks, comprising:
receiving a physical secure erase command;
performing an erase operation to the memory cells of the blocks;
performing a memory programming operation to the memory cells of the blocks;
performing an identification operation to find one or more failed memory cells of the blocks; and
performing a select gate programming operation to a plurality of select gates only to a portion of the blocks comprising the one or more failed memory cells.
2. The method of claim 1 , wherein the performing the select gate programming operation to the plurality of select gates comprises programming a threshold voltage of select gate drains greater than a read level.
3. The method of claim 1 , wherein the performing the select gate programming operation to the plurality of select gates comprises programming a threshold voltage of select gate sources greater than a read level.
4. The method of claim 1 , wherein the performing the select gate programming operation to the plurality of select gates comprises a programming threshold voltage of select gate sources and select gate drains greater than a read level.
5. The method of claim 1 , wherein the performing the identification operation to find one or more failed memory cells of the blocks comprises identifying one or more failed erased memory cells from the performing the erase operation.
6. The method of claim 1 , wherein the performing the identification operation to find one or more failed memory cells of the blocks comprises identifying one or more failed programmed memory cells from the performing the memory programming operation.
7. A solid state drive, comprising:
a controller;
a plurality of blocks having a plurality of NAND strings, each NAND string comprises a select gate drain, a plurality of memory cells, and a select gate source connected in series;
a memory erasing instruction that, when executed by the controller, cause the controller to:
perform an erase operation to the memory cells of the blocks;
program the memory cells of the blocks;
identify one or more failed memory cells of the blocks; and
increase a threshold voltage to one or more of a select gates selected from the group consisting of select gate drain and select gate source only from a portion of the NAND strings, wherein the portion of the NAND strings comprises the one or more failed memory cells.
8. The solid state drive of claim 7 , wherein the threshold voltage of select gates is programmed higher than a read level.
9. The solid state drive of claim 7 , wherein the threshold voltage of select gate drains is programmed higher than a read level.
10. The solid state drive of claim 7 , wherein the threshold voltage of select gate sources is programmed higher than a read level.
11. The solid state drive of claim 7 , wherein the threshold voltage of select gate drains and select gate sources is programmed out of a read level.
12. A non-transitory computer readable storage medium containing instructions that, when executed by a controller, performs the following method for erasing a solid state drive:
performing an erase operation to a plurality of memory cells of a plurality of blocks;
performing a flash write operation to the memory cells of the blocks;
performing an identification operation to find a portion of the blocks that is bad; and
increasing a threshold voltage of a plurality of select gates only the portion of the blocks that is bad.
13. The non-transitory computer readable storage medium of claim 12 , wherein the threshold voltage of select gates is programmed higher than a read level.
14. The non-transitory computer readable storage medium of claim 12 , wherein the threshold voltage of select gate drains is programmed out of a read level.
15. The non-transitory computer readable storage medium of claim 12 , wherein the threshold voltage of select gate sources is programmed out of a read level.
16. The non-transitory computer readable storage medium of claim 12 , wherein the threshold voltage of select gate drains and select gate sources is programmed out of a read level.