Memory failure detection and resource allocation
View Patent ↗The present disclosure is directed to a device, a method, and a non-transitory computer readable medium for determining a level of uncertainty of programmed states of memory cells. In one aspect, a memory device includes memory cells, an uncertainty prediction circuit coupled to the memory cells, and a data conversion circuit coupled to the memory cells. The uncertainty prediction circuit is configured to determine, from a subset of the memory cells coupled to a word line, a number of memory cells having a predetermined state. The data conversion circuit is configured to apply a data conversion to a portion of data stored by the subset of the memory cells, in response to the uncertainty prediction circuit determining that the number of memory cells is between a first threshold and a second threshold.
1. A memory device comprising:
memory cells;
an uncertainty prediction circuit coupled to the memory cells, the uncertainty prediction circuit configured to determine, from a subset of the memory cells coupled to a word line, a number of memory cells having a predetermined state; and
a data conversion circuit coupled to the memory cells, the data conversion circuit configured to apply a data conversion to a portion of data stored by the subset of the memory cells in response to the uncertainty prediction circuit determining that the number of memory cells is between a first threshold and a second threshold.
2. The memory device of claim 1 , further comprising an additional data conversion circuit coupled to the memory cells, the additional data conversion circuit configured to:
apply a different data conversion to the portion of the data stored by the subset of the memory cells, in response to the uncertainty prediction circuit determining that the number of memory cells is between the second threshold and a third threshold.
3. The memory device of claim 1 , wherein the predetermined state of a memory cell indicates that the memory cell is erased, the memory device further comprising a memory status indication circuit coupled to the uncertainty prediction circuit, the memory status indication circuit configured to:
in response to the uncertainty prediction circuit determining that the number of memory cells is less than the first threshold, generate a status indicator indicating that the subset of the memory cells is programmable.
4. The memory device of claim 1 , wherein the predetermined state of a memory cell indicates that the memory cell is erased, the memory device further comprising a memory status indication circuit coupled to the uncertainty prediction circuit, the memory status indication circuit configured to:
in response to the uncertainty prediction circuit determining that the number of memory cells is more than a third threshold, generate a status indicator indicating that the memory cells in a block are not programmable.
5. The memory device of claim 1 , wherein each memory cell is configured to store a first page data, a second page data, and a third page data, the portion of the data stored by the subset of the memory cells being the third page data stored by the subset of the memory cells.
6. The memory device of claim 5 , wherein the data conversion circuit is further configured to perform, for each memory cell in the subset of the memory cells, an XOR operation on the first page data and the second page data to substitute the third page data of the memory cell.
7. The memory device of claim 5 , further comprising an additional data conversion circuit coupled to the memory cells, the additional data conversion circuit configured to:
reset the third page data stored by the subset of the memory cells, in response to the uncertainty prediction circuit determining that the number of memory cells is between the second threshold and a third threshold higher than the second threshold.
8. The memory device of claim 5 , further comprising a memory state distribution analysis circuit coupled to the memory cells, the memory state distribution analysis circuit configured to:
determine a distribution of memory states of another subset of the memory cells coupled to another word line, the another subset of the memory cells adjacent to the subset of the memory cells; and
determine another distribution of memory states of the subset of the memory cells coupled to the word line,
wherein the uncertainty prediction circuit is configured to determine, from the subset of the memory cells coupled to the word line, the number of memory cells having the predetermined state, in response to the memory state distribution analysis circuit determining that:
the distribution of the memory states of the another subset of the memory cells is substantially equal to a predetermined distribution, and the another distribution of the memory states of the subset of the memory cells is
different from the predetermined distribution.
9. A memory device comprising:
memory cells;
an uncertainty prediction circuit coupled to the memory cells and configured to determine, from a subset of the memory cells coupled to a word line, a number of memory cells having an erased state; and
a data conversion circuit configured to apply a data conversion to a portion of data stored by the subset of the memory cells in response to the uncertainty prediction circuit determining that the number of erased memory cells is between a first threshold and a second threshold.
10. The memory device of claim 9 , further comprising an additional data conversion circuit coupled to the memory cells and configured to:
apply a different data conversion to the portion of the data stored by the subset of the memory cells, in response to the uncertainty prediction circuit determining that the number of erased memory cells is between the second threshold and a third threshold.
11. The memory device of claim 9 , further comprising a memory status indication circuit coupled to the uncertainty prediction circuit, the memory status indication circuit configured to:
in response to the uncertainty prediction circuit determining that the number of erased memory cells is less than the first threshold, generate a status indicator indicating that the subset of the memory cells is programmable.
12. The memory device of claim 9 , further comprising a memory status indication circuit coupled to the uncertainty prediction circuit, the memory status indication circuit configured to:
in response to the uncertainty prediction circuit determining that the number of erased memory cells is more than a third threshold, generate a status indicator indicating that the memory cells in a block are not programmable.
13. The memory device of claim 9 , wherein each memory cell is configured to store a first page data, a second page data, and a third page data, the portion of the data stored by the subset of the memory cells being the third page data stored by the subset of the memory cells.
14. The memory device of claim 13 , wherein the data conversion circuit is further configured to perform, for each memory cell in the subset of the memory cells, an XOR operation on the first page data and the second page data to substitute the third page data of the memory cell.
15. The memory device of claim 13 , further comprising an additional data conversion circuit coupled to the memory cells and configured to:
reset the third page data stored by the subset of the memory cells, in response to the uncertainty prediction circuit determining that the number of erased memory cells is between the second threshold and a third threshold higher than the second threshold.
16. The memory device of claim 13 , further comprising a memory state distribution analysis circuit coupled to the memory cells and configured to:
determine a distribution of memory states of another subset of the memory cells coupled to another word line, the another subset of the memory cells adjacent to the subset of the memory cells; and
determine another distribution of memory states of the subset of the memory cells coupled to the word line,
wherein the uncertainty prediction circuit is configured to determine, from the subset of the memory cells coupled to the word line, the number of memory cells having the erased state, in response to the memory state distribution analysis circuit determining that:
the distribution of the memory states of the another subset of the memory cells is substantially equal to a predetermined distribution, and the another distribution of the memory states of the subset of the memory cells is different from the predetermined distribution.
17. A memory device comprising:
memory cells;
means for determining, from a subset of the memory cells coupled to a word line, a number of memory cells having a predetermined state; and
means for applying a data conversion to a portion of data stored by the subset of the memory cells in response to the uncertainty prediction circuit determining that the number of memory cells is between a first threshold and a second threshold.
18. The memory device of claim 17 , further comprising:
means for applying a different data conversion to the portion of the data stored by the subset of the memory cells, responsive to the determining means determining that the number of memory cells is between the second threshold and a third threshold.
19. The memory device of claim 17 , wherein the predetermined state of a memory cell indicates that the memory cell is erased, the memory device further comprising:
means for generating, responsive to the determining means determining that the number of memory cells is less than the first threshold, a status indicator indicating that the subset of the memory cells is programmable.
20. The memory device of claim 17 , wherein the predetermined state of a memory cell indicates that the memory cell is erased, the memory device further comprising:
means for generating, responsive to the determining means determining that the number of memory cells is more than a third threshold, a status indicator indicating that the memory cells in a block are not programmable.