Mechanism to improve driver capability with fine tuned calibration resistor
Aspects of a storage device including a controller, a calibration resistor and a die having an output driver and a calibration circuit are provided, which allow for an output impedance of the output driver to be calibrated to a lower impedance than a minimum required for reading data across PVT variations of the die at maximum loading of the controller. To check whether slow corners may operate using the lower impedance, the controller determines whether the output impedance of the output driver can be calibrated to the lower impedance at a maximum temperature and minimum voltage applied to the die, or whether a calibration code generated from the calibration circuit exceeds a threshold at a nominal temperature and voltage applied to the die. Thus, slow corners are screened out from lower impedance use, while faster devices are designed with a smaller calibration resistance to benefit from increased memory and speed.
1. A storage device, comprising:
a calibration resistor having a resistance that enables a calibration circuit to calibrate an output impedance of an output driver to a lower impedance than a minimum impedance, the minimum impedance being required by a controller to read stored data across process, voltage and temperature variations of a die at maximum loading of the controller.
2. The storage device of claim 1 , further comprising the controller configured to command the calibration circuit to calibrate the output impedance.
3. The storage device of claim 1 , wherein the output driver further comprises a plurality of parallel pull-up driver transistors and a plurality of parallel pull-down driver transistors, and wherein the calibration circuit is further configured to set an impedance of the parallel pull-up driver transistors and an impedance of the parallel pull-down driver transistors to the resistance of the calibration resistor.
4. The storage device of claim 3 , wherein the output driver further comprises a plurality of parallel second pull-up driver transistors coupled in parallel with the pull-up driver transistors and a plurality of parallel second pull-down driver transistors coupled in parallel with the pull-down driver transistors, and wherein the calibration circuit is further configured to set an impedance of the parallel second pull-up driver transistor and an impedance of the parallel second pull-down driver transistor to the resistance of the calibration resistor.
5. The storage device of claim 1 , wherein the output driver further comprises a plurality of parallel pull-up driver transistors and a plurality of parallel pull-down driver transistors, and wherein the calibration circuit is further configured to control the output impedance of the output driver by controlling the pull-up driver transistors and the pull-down driver transistors.
6. The storage device of claim 5 , wherein the calibration circuit comprises a plurality of parallel pull-up calibration transistors, the calibration circuit being further configured to control the pull-up calibration transistors based on the calibration resistor and control the pull-up driver transistors based on the control of the pull-up calibration transistors.
7. The storage device of claim 6 , wherein the calibration circuit comprises an output pulled up by the pull-up calibration transistors and loaded by the calibration resistor, the calibration circuit further comprising a feedback circuit configured to control the pull-up calibration transistors based on the output of the calibration circuit.
8. The storage device of claim 7 , wherein the feedback circuit is configured to set an impedance of the parallel pull-up calibration transistors to the resistance of the calibration resistor.
9. A storage device, comprising:
a controller configured to determine whether an output impedance of an output driver can be calibrated to an impedance lower than a threshold when a die has a maximum temperature and a minimum voltage.
10. The storage device of claim 9 , further comprising a calibration resistor, wherein the calibration resistor has a resistance that would enable a calibration circuit to calibrate the output impedance to a lower impedance than a minimum impedance, the minimum impedance being required by the controller to read stored data across process, voltage and temperature variations of the die at maximum loading of the controller.
11. The storage device of claim 9 , wherein the controller is configured to command a calibration circuit to calibrate the output impedance.
12. The storage device of claim 9 , wherein the threshold is a function of a resistance of a calibration resistor.
13. The storage device of claim 9 , further comprising a calibration circuit, wherein the output driver further comprises a plurality of parallel pull-up driver transistors and a plurality of parallel pull-down driver transistors, and wherein the calibration circuit is further configured to set an impedance of the parallel pull-up driver transistors and an impedance of the parallel pull-down driver transistors to a resistance of a calibration resistor.
14. A storage device, comprising:
a controller configured to determine whether a calibration code exceeds a threshold when a die has a nominal temperature and a nominal voltage.
15. The storage device of claim 14 , further comprising a calibration resistor, wherein the calibration resistor has a resistance that would enable a calibration circuit to calibrate an output impedance of an output driver to a lower impedance than a minimum impedance, the minimum impedance being required by the controller to read stored data across process, voltage and temperature variations of the die at maximum loading of the controller.
16. The storage device of claim 14 , wherein the controller is configured to command a calibration circuit to calibrate an output impedance of an output driver.
17. The storage device of claim 14 , further comprising an output driver and a calibration circuit, wherein the output driver further comprises a plurality of parallel pull-up driver transistors and a plurality of parallel pull-down driver transistors, and wherein the calibration circuit is further configured to set an impedance of the parallel pull-up driver transistors and an impedance of the parallel pull-down driver transistors to a resistance of a calibration resistor.
18. The storage device of claim 14 , further comprising a calibration circuit, wherein the calibration circuit comprises an output loaded by a calibration resistor, a plurality of pull-up calibration transistors pulling up the output, and a feedback circuit configured to generate the calibration code based on the output of the calibration circuit.
19. The storage device of claim 18 , wherein the feedback circuit is further configured to control the pull-up calibration transistors with the calibration code.
20. The storage device of claim 14 , further comprising an output driver and a calibration circuit, wherein the output driver further comprises a plurality of parallel pull-up driver transistors and a plurality of parallel pull-down driver transistors, and wherein the calibration circuit is further configured to control the parallel pull-up driver transistors and the parallel pull-down driver transistors with the calibration code.