IP Library Granted Patent US 11,437,104
Granted Patent B2
US 11,437,104 · App. 17/181,709 · Granted Sep 6, 2022

Storage system and method for a hybrid quad-level cell (QLC) write scheme for reduced random access memory (RAM) footprint

Inventors: Amit Sharma (Karnataka, IN); Sourabh Sankule (Karnataka, IN); Dinesh Kumar Agarwal (Karnataka, IN); Chetan Agrawal (Karnataka, IN)
Assignee: Western Digital Technologies, Inc.
G11C16/10G11C16/26G11C16/3459
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Quick Facts
Patent No.
US 11,437,104
App. No.
17/181,709
Granted
Sep 6, 2022
Kind
B2
Abstract

A storage system and method for a hybrid quad-level cell (QLC) write scheme for reduced random access memory (RAM) footprint and better performance are provided. In one example, a storage system includes a volatile memory and a non-volatile memory. A Foggy program operation is performed in a QLC memory in the non-volatile memory by writing two pages of data into the QLC memory. Then, a Fine program operation is performed in the QLC memory by reading the two pages of data written to the QLC memory in the Foggy program operation, reading two other pages of data from the volatile memory, and writing the two pages of data read from the QLC memory and the two other pages of data read from the volatile memory in the QLC memory.

Claims (43)

1. A storage system comprising:

a volatile memory;

a non-volatile memory; and

a controller configured to:

perform a Foggy program operation in a multi-level cell (MLC) memory in the non-volatile memory by writing in the MLC memory only a part of a set of data to be written in the MLC memory; and

perform a Fine program operation in the MLC memory by:

reading the part of the set of data written in the MLC memory;

reading a rest of the set of data from the volatile memory; and

writing, in the MLC memory, the part of the set of data read from the MLC memory and the rest of the set of data read from the volatile memory.

2. The storage system of claim 1 , wherein the multi-level memory cell comprises a quad-level memory cell.

3. The storage system of claim 2 , wherein the part of the set of data comprises lower and middle pages of data.

4. The storage system of claim 2 , wherein the rest of the set of data comprises upper and top pages.

5. The storage system of claim 1 , wherein the part of the set of data is read from the MLC memory using an internal data load (IDL) read operation.

6. The storage system of claim 1 , wherein the non-volatile memory comprises a three-dimensional memory.

7. In a storage system comprising a memory and a controller, a method comprising:

receiving incoming data from a host to be written in the memory;

determining whether usage of single-level cell (SLC) memory in the memory is below a threshold; and

in response to determining that usage of the SLC memory in the memory is not below the threshold:

sensing a page of data from the SLC memory; and

writing the sensed page of data and a page of data from the incoming data in a multi-level cell (MLC) memory in the memory.

8. The method of claim 7 , further comprising:

in response to determining that usage of the SLC memory in the memory is below the threshold, writing the incoming data to the SLC memory.

9. The method of claim 7 , wherein the MLC memory comprises a quad-level cell (QLC) memory.

10. The method of claim 9 , wherein the page of data sensed from the SLC memory comprises a lower or a middle page of data.

11. The method of claim 9 , wherein the page of data from the incoming data comprises an upper or a top page.

12. The method of claim 7 , wherein the page of data is sensed using an internal data load (IDL) read operation.

13. The method of claim 7 , wherein the threshold varies between programs.

14. The method of claim 7 , wherein the threshold varies depends on a number of SLC blocks that can be allocated in a program.

15. The method of claim 7 , further comprising

sensing a page of data from the MLC memory; and

writing the sensed page of data from the SLC memory, the sensed page of data from the MLC memory, and the page of data from the incoming data in the MLC memory.

16. A storage system comprising:

a volatile memory;

a non-volatile memory;

means for performing a Foggy program operation in a quad-level cell memory in the non-volatile memory by writing two pages of data into the quad-level cell memory; and

means for performing a Fine program operation in the quad-level cell memory by:

reading the two pages of data written to the quad-level cell memory in the Foggy program operation;

reading two other pages of data from the volatile memory; and

writing the two pages of data read from the quad-level cell memory and the two other pages of data read from the volatile memory in the quad-level cell memory.

17. The storage system of claim 16 , wherein the two pages of data written in the Foggy program operation comprise lower and middle pages.

18. The storage system of claim 16 , wherein the two other pages of data comprise upper and top pages.

19. The storage system of claim 16 , wherein the two pages of data are read from the quad-level cell memory using an internal data load (IDL) read operation.

20. The storage system of claim 16 , wherein the non-volatile memory comprises a three-dimensional memory.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2021
From: SHARMA, AMIT; SANKULE, SOURABH; AGARWAL, DINESH KUMAR; AGRAWAL, CHETAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055357/0048 →