Granted Patent B2

US 8,806,116 · App. 12/369,725 · Granted Aug 12, 2014

Abstract

Claims (106)

1. A memory module comprising:

a printed circuit board (PCB) with an edge connector;

an address controller integrated circuit coupled to the PCB and the edge connector, the address controller integrated circuit to determine if an address is associated with a compound memory request for the memory module, wherein a compound memory request includes an aggregation of a plurality of memory accesses; and

a plurality of memory slices, each memory slice of the plurality of memory slices including

a plurality of read-writeable non-volatile memory integrated circuits coupled to the PCB; and

a slave memory controller integrated circuit coupled to the PCB and the edge connector, the slave memory controller integrated circuit further coupled between the address controller integrated circuit and the plurality of read-writeable non-volatile memory integrated circuits, the slave memory controller integrated circuit to receive a memory slice request from the address controller integrated circuit in response to the compound memory request, the slave memory controller integrated circuit to selectively activate one or more of the plurality of read-writeable non-volatile memory integrated circuits in the respective memory slice in response to an address received from the address controller integrated circuit, and the slave memory controller integrated circuit further to selectively read from or write data into selected memory locations in the one or more of the plurality of read-writeable non-volatile memory integrated circuits in response to the memory slice request.

2. The memory module of claim 1 , wherein

each slave memory controller integrated circuit further to remap a received address from the address controller integrated circuit into a slice address for the one or more of the plurality of read-writeable non-volatile memory integrated circuits in its respective memory slice.

3. The memory module of claim 2 , wherein

each slave memory controller integrated circuit includes an address remapper to remap the received address from the address controller integrated circuit into a plurality of memory IC addresses associated with a respective one or more of the plurality of read-writeable non-volatile memory integrated circuits in its respective memory slice to access memory locations in each.

4. The memory module of claim 3 , wherein

the address remapper maps out a physical memory location in a read-writeable non-volatile memory integrated circuit of a memory slice to avoid bad blocks.

5. The memory module of claim 3 , wherein

different memory locations are accessed in the read-writeable non-volatile memory integrated circuits across the memory slices of the memory module to pack memory responses from each memory slice on the memory module together as one memory module response.

6. The memory module of claim 2 , wherein

each slave memory controller integrated circuit includes a register to store the address from the address controller integrated circuit to selectively access one or more of the plurality of read-writeable non-volatile memory integrated circuits in its slice over one or more next memory access transactions.

7. The memory module of claim 1 , wherein

each slave memory controller integrated circuit includes an address/control decoder to receive an address including a plurality of mask bits, the address/control decoder to decode the mask bits to selectively activate one or more of the plurality of read-writeable non-volatile memory integrated circuits in its slice.

8. The memory module of claim 7 , wherein

each slave memory controller integrated circuit further includes a second register to store the address from the address controller integrated circuit to selectively access one or more of the plurality of read-writeable non-volatile memory integrated circuits in its slice over one or more next memory access transactions.

9. The memory module of claim 1 , wherein

each slave memory controller integrated circuit includes a first register to store one or more mask bits to selectively activate one or more of the plurality of read-writeable non-volatile memory integrated circuits in its slice over one or more next memory access transactions.

10. The memory module of claim 9 , wherein

each slave memory controller integrated circuit further includes a second register to store the address from the address controller integrated circuit to selectively access one or more of the plurality of read-writeable non-volatile memory integrated circuits in its slice over one or more next memory access transactions.

11. The memory module of claim 1 , wherein

the memory module is a dual inline memory module with at least one read-writeable non-volatile memory integrated circuit coupled to a front side of the PCB and at least one read-writeable non-volatile memory integrated circuit coupled to a back side of the PCB and with at least one slave memory controller integrated circuit coupled to the front side of the PCB and at least one slave memory controller integrated circuit coupled to the back side of the PCB; and

the edge connector is a DIMM connector with pads on the front side of the PCB and pads on the back side of the PCB to respectively couple to the at least one slave memory controller integrated circuit coupled to the front side and the at least one slave memory controller integrated circuit coupled to the back side of the PCB.

12. The memory module of claim 1 , wherein

the plurality of read-writeable non-volatile memory integrated circuits are NAND-gate electrically erasable programmable read only memory (EEPROM) integrated circuits, NOR-gate EEPROM integrated circuits, or a combination thereof.

13. The memory module of claim 1 , wherein

each slave memory controller integrated circuit further includes

a first bidirectional bus multiplexer to couple to the plurality of read-writeable non-volatile memory integrated circuits and multiplex data between data buses; and

a second bidirectional bus multiplexer to couple to the edge connector and multiplex data between data buses;

wherein a width of a data bus from the slave memory controller integrated circuit to the plurality of read-writeable non-volatile memory integrated circuits differs from a width of the data bus from the slave memory controller integrated circuit to the edge connector.

14. The memory module of claim 1 , wherein

the first and second bus multiplexers of the slave memory controller integrated circuit include

a read buffer for read accesses and a write buffer for write accesses so that speeds between buses may differ.

15. The memory module of claim 1 , wherein

the slave memory controller integrated circuit is packaged together with one or more one or more of the plurality of read-writeable non-volatile memory integrated circuits into a multichip integrated circuit package.

16. The memory module of claim 1 , wherein

each slave memory controller integrated circuit includes

a block move engine, and

a volatile random access memory (VRAM) coupled to the block move engine to provide a shared memory region,

wherein the block move engines and the VRAM to provide data burst accesses over the edge connector of the memory module and a plurality of block memory access transactions with one or more of the plurality of read-writeable non-volatile memory integrated circuits.

17. The memory module of claim 16 , wherein

each slave memory controller integrated circuit further includes

a loadable counter to store and automatically increment the address from the address controller integrated circuit to selectively access one or more locations in the shared memory region in the VRAM over a plurality of cycles to access blocks of data for a data burst.

18. The memory module of claim 1 , wherein

the slave memory controller integrated circuit further includes a processor and a scratch pad memory coupled to the processor.

19. The memory module of claim 1 , wherein

each slave memory controller integrated circuit is synchronized together to perform per slice memory transactions initiated by instructions received by the address controller integrated circuit over the edge connector, and

each slave memory controller integrated circuit further to pack per slice block responses together to concurrently provide a memory module response over the edge connector.

20. The memory module of claim 1 , wherein

each slave memory controller integrated circuit further generates one or more enable signals respectively for one or more of the plurality of read-writeable non-volatile memory integrated circuits to selectively enable or disable each read-writeable non-volatile memory integrated circuit.

21. A memory module comprising:

a printed circuit board (PCB) with an edge connector;

an address controller coupled to the PCB and the edge connector; and

a plurality of memory slices, each memory slice including

one or more read-writeable non-volatile memory integrated circuits coupled to the PCB, and

a slave memory controller coupled to the PCB, the edge connector and the one or more read-writeable non-volatile memory integrated circuits, the slave memory controller to receive a memory slice request from the address controller in response to a compound memory request, the slave memory controller to selectively activate one or more of the one or more read-writeable non-volatile memory integrated circuits in the respective memory slice in response to an address received from the address controller to selectively read from or write data into selected memory locations in the one or more read-writeable non-volatile memory integrated circuits;

a DC power supply voltage converter to convert power supply voltages of the edge connector to higher power supply voltages of the read-writeable non-volatile memory integrated circuits; and

wherein each slave memory controller further includes

a voltage level translator to provide voltage level translation between logic level signals at the edge connector and logic level signals at the read-writeable non-volatile memory integrated circuits.

22. The memory module of claim 21 , wherein

each slave memory controller includes

a block move engine, and

a volatile random access memory (VRAM) coupled to the block move engine to provide a shared memory region,

wherein the block move engines and the VRAM to provide data burst accesses over the edge connector of the memory module and a plurality of block memory access transactions with the read-writeable non-volatile memory integrated circuits.

23. The memory module of claim 22 , wherein

each slave memory controller further includes a loadable counter to store and automatically increment the address from the address controller to selectively access one or more locations in the shared memory region in the VRAM over a plurality of cycles to access blocks of data for a data burst.

24. The memory module of claim 21 , wherein

the slave memory controller further includes a processor and a scratch pad memory coupled to the processor.

25. The memory module of claim 21 , wherein

each slave memory controller is synchronized together to perform per slice memory transactions initiated by instructions received by the address controller over the edge connector, and

each slave memory controller further to pack per slice block responses together to concurrently provide a memory module response over the edge connector.

26. A dual inline memory module (DIMM) comprising:

a printed circuit board with an edge connector;

an address controller integrated circuit coupled to the printed circuit board and the edge connector, the address controller integrated circuit to determine if address and control signals indicate memory access requests for the DIMM;

a plurality of memory slices, each memory slice of the plurality of memory slices including

a plurality of read-writeable non-volatile memory integrated circuits coupled to the printed circuit board;

a slave memory controller integrated circuit coupled to the printed circuit board and the edge connector, the slave memory controller integrated circuit further coupled between the address controller integrated circuit and the plurality of read-writeable non-volatile memory integrated circuits, the slave memory controller integrated circuit to receive the memory access requests for the DIMM from the address controller integrated circuit, the slave memory controller integrated circuit to selectively activate one or more of the plurality of read-writeable non-volatile memory integrated circuits (ICs) in the slice in response to the address received from the address controller integrated circuit to read or write data into selected memory locations in one or more of the plurality of read-writeable non-volatile memory integrated circuits of the respective memory slice; and

a memory slice processor coupled to the slave memory controller integrated circuit, the memory slice processor to execute instructions and perform operations on data stored in the respective memory slice.

27. The DIMM of claim 26 , wherein

each slave memory controller integrated circuit is synchronized together to perform per slice memory access transactions initiated by instructions received by the address controller integrated circuit over the edge connector and to pack per slice block responses together to concurrently provide a DIMM response over the edge connector.

28. The DIMM of claim 27 , wherein

at least one memory slice does not participate in the memory module operation or its memory access operation is incomplete, and

the slave memory controller integrated circuit generates a known null data for the at least one memory slice to be packed together to form the DIMM response over the edge connector.

29. The DIMM of claim 26 , wherein

each slave memory controller integrated circuit includes a volatile random access memory providing a shared memory region between the memory slice processor and a system processor coupled to the edge connector to communicate commands and receive responses.

30. The DIMM of claim 29 , wherein

each slave memory controller integrated circuit further includes

collision detection logic to detect simultaneous requests to one or more of the plurality of read-writeable non-volatile memory integrated circuits by the memory slice processor and the system processor, and

an arbiter to arbitrate access between the memory slice processor and the system processor to the plurality of read-writeable non-volatile memory integrated circuits.

31. The DIMM of claim 30 , wherein

each slave memory controller integrated circuit further includes

a variable latency processor interface coupled to the processor, and

the arbiter controls the processor interface to introduce wait states into the processor access cycle to avoid collisions from simultaneous requests to access one or more of the plurality of read-writeable non-volatile memory integrated circuits.

32. The DIMM of claim 30 , wherein

the memory slice processor is a general purpose programmable processor.

33. The DIMM of claim 30 , wherein

each memory slice further includes

a scratch pad memory coupled to the memory slice processor, the memory slice processor to execute instructions stored in the scratch pad memory and process data in response to the instructions.

34. The DIMM of claim 33 , wherein

the slave memory controller integrated circuit, the memory slice processor, and the scratch pad memory are packaged together in a multi-chip module package.

35. The DIMM of claim 26 , wherein

each slave memory controller integrated circuit further generates one or more enable signals respectively for one or more of the plurality of read-writeable non-volatile memory integrated circuits to selectively enable or disable each read-writeable non-volatile memory integrated circuit.

Assignments (12)