IP Library Granted Patent US 8,245,000
Granted Patent B2
US 8,245,000 · App. 11/436,845 · Granted Aug 14, 2012

System and method for managing security of a memory device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,245,000
App. No.
11/436,845
Granted
Aug 14, 2012
Kind
B2
Abstract

A computing device and method for managing security of a memory or storage device without the need for administer privileges. To access the secure memory, a host provides a data block containing a control command and authentication data to the memory device. The memory device includes a controller for controlling access to a secure memory in the memory device. The memory device identifies the control command in the data block, authenticates the control command based on the authentication data, and executes the control command to allow the host device to access the secure memory.

Claims (35)

1. A memory device comprising:

a first memory; and

a controller coupled to the first memory, the controller configured to provide control instructions to a host device, receive at least one data block comprising a control command and authentication data from the host device, authenticate the data block based on the authentication data, identify the control command, and set a mode of the memory device to control access to the first memory by subsequent input-output commands from the host device based on the control command,

wherein the control instructions comprise an executable file and an initiation file, wherein the executable file is executable by the host device to generate the at least one data block, and wherein the initiation file identifies an icon for display in association with the executable file when the memory device is in a locked mode and not for display when the memory device is in an unlocked mode.

2. The memory device of claim 1 , wherein the controller is further configured to initially prevent access to the first memory, the controller further configured to execute the control command to allow access to the first memory.

3. The memory device of claim 1 , wherein the authentication data includes a file signature.

4. The memory device of claim 1 , wherein the authentication data includes a password.

5. The memory device of claim 1 , wherein the first memory is a flash memory.

6. The memory device of claim 1 , further comprising a second memory coupled to the controller, wherein the controller is further configured to control access to the second memory.

7. The memory device of claim 1 , further comprising a second memory coupled to the controller, the second memory comprising a first file allocation table for the first memory, the controller further configured to control access to the first memory by controlling access to the first file allocation table.

8. The memory device of claim 7 , wherein the controller is further configured to prevent access to the first memory by preventing access to the first file allocation table.

9. The memory device of claim 7 , further comprising a third memory coupled to the controller, the second memory further comprising a second file allocation table for the third memory.

10. The method of claim 1 , wherein the control command sets the mode of the memory device to an unlocked mode that allows access to the first memory by the subsequent input-output commands.

11. A memory device for storing data of a host device, comprising:

a memory unit comprising a first memory and a second memory; and

a controller coupled to the memory unit, the controller configured to provide control instructions to the host device, receive at least one data block comprising a control command and authentication data from the host device, allow the host device to access the first memory, authenticate the at least one data block based on the authentication data, identify the control command, and set a mode of the memory device to control access from the host device to the second memory by subsequent input-output commands based on the control command,

wherein the control instructions comprise an executable file and an initiation file, wherein the executable file is executable by the host device to generate the at least one data block, and wherein the initiation file identifies an icon for display in association with the executable file when the memory device is in a locked mode and not for display when the memory device is in an unlocked mode.

12. The memory device of claim 11 , wherein the controller is configured to initially prevent the host device from accessing the second memory, the controller further configured to subsequently execute the control command to allow the host device to access the second memory with subsequent input-output commands.

13. The memory device of claim 12 , wherein the memory unit further comprises a third memory, the third memory configured to store a first file allocation table for the first memory and a second file allocation table for the second memory.

14. The memory device of claim 13 , wherein the controller is further configured to prevent the host device from accessing the second memory by preventing the host device from accessing the second file allocation table.

15. The memory device of claim 13 , wherein the third memory is further configured to store a partition table for allocating a portion of the memory unit to the first memory and another portion of the memory unit to the second memory.

16. A method of managing security of a memory device, comprising:

preventing a host device from accessing a first memory of the memory device;

providing control instructions to the host device;

receiving at least one data block comprising a control command and authentication data from the host device, wherein the control instructions comprise an executable file and an initiation file, wherein the executable file is executable by the host device to generate the at least one data block, and wherein the initiation file identifies an icon for display in association with the executable file when the memory device is in a locked mode and not for display when the memory device is in an unlocked mode;

authenticating the at least one data block based on the authentication data;

identifying the control command in the at least one data block; and

executing the control command to set a mode of the memory device to allow the host device to access the first memory using subsequent input-output commands.

17. The method of claim 16 , further comprising:

receiving an indicator in the memory device; and

preventing the host device from accessing the first memory in response to receiving the indicator.

18. The method of claim 17 , wherein the indicator indicates that the memory device is disconnected from the host device.

19. The method of claim 17 , wherein the indicator indicates that power is cycled in the memory device.

20. The method of claim 16 , wherein authenticating the at least one data block based on the authentication data comprises authenticating a signature in the at least one data block.

21. The method of claim 16 , wherein the first memory comprises flash memory.

Assignments (11)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2018
From: HGST TECHNOLOGIES SANTA ANA, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046174/0446 →
CHANGE OF NAME Recorded Jul 1, 2015
From: STEC, INC.
To: HGST TECHNOLOGIES SANTA ANA, INC.
Reel/Frame 036042/0390 →