Adaptive bit-flipping decoder based on dynamic error information
View Patent ↗A device includes a comparator configured to select a first threshold in response to a value of a variable node indicating a first logical value and to select a second threshold in response to the value of the variable node indicating a second logical value. The device also includes a variable node update circuit configured to adjust the value of the variable node in response to a number of unsatisfied check nodes associated with the variable node satisfying the selected threshold.
1. A device comprising:
a comparator configured to select a first threshold in response to a value of a variable node indicating a first logical value and to select a second threshold in response to the value of the variable node indicating a second logical value; and
a variable node update circuit configured to adjust the value of the variable node in response to a number of unsatisfied check nodes associated with the variable node satisfying the selected threshold.
2. The device of claim 1 . further comprising:
a memory; and
a bit-flipping error correction code (ECC) decoder configured to perform a bitflipping decoding operation on a representation of a codeword read from the memory, the bit-flipping ECC decoder comprising:
the comparator; and
the variable node update circuit.
3. The device of claim 2 , further comprising syndrome circuitry configured to determine, for each particular variable node of a plurality of variable nodes, a number of unsatisfied check nodes associated with the particular variable node.
4. The device of claim 1 , further comprising error detection circuitry configured to determine, based on one or more codewords read from a memory, a first count of erroneous bits having the first logical value and a second count of erroneous bits having the second logical value, wherein the comparator is further configured to select the first threshold based further on a first error rate based at least in part on the first count and to select the second threshold based further on a second error rate based at least in part on the second count.
5. The device of claim 4 , wherein the error detection circuitry is further configured to determine, based on the one or more codewords, a third count of unreliable correct bits having the first logical value and a fourth count of unreliable correct bits having the second logical value, wherein the comparator is further configured to select the first threshold based further on the third count and to select the second threshold based further on the fourth count.
6. The device of claim 1 , further comprising:
a first set of thresholds associated with the first logical value; and
a second set of thresholds associated with the second logical value.
7. The device of claim 6 , wherein the comparator is further configured to:
select the first set of thresholds or the second set of thresholds based on the value of the variable node; and
retrieve the selected threshold from the selected set of thresholds.
8. The device of claim 7 , wherein the comparator is further configured to perform a look-up operation to retrieve the selected threshold from the selected set of thresholds based on a count of cycles of a decoder clock.
9. The device of claim 6 , further comprising:
a third set of thresholds associated with the first logical value; and
a fourth set of thresholds associated with the second logical value.
10. The device of claim 9 , wherein the comparator is further configured to:
select the first set of thresholds, the second set of thresholds, the third set of thresholds, or the fourth set of thresholds based on the value of the variable node-and further based on a reliability indicator associated with the value; and
retrieve the selected threshold from the selected set of thresholds.
11. The device of claim 10 , wherein:
the value of the variable node-corresponds to a hard bit value; and
the reliability indicator corresponds to a soft bit value.
12. A method comprising:
selecting, at a bit-flipping decoder:
a first threshold in response to a value of a variable node indicating a first logical value; or
a second threshold in response to the value of the variable node indicating a second logical value; and
adjusting the value of the variable node in response to a number of unsatisfied check nodes associated with the variable node satisfying the selected threshold.
13. The method of claim 12 , further comprising:
determining one or more bit counts based on one or more codewords read from a memory, the one or more bit counts including a first count of erroneous bits having the first logical value and a second count of erroneous bits having the second logical value;
selecting a first set of thresholds or a second set of thresholds based on the value of the variable node, the first set of thresholds associated with the first logical value and the first count, and the second set of thresholds associated with the second logical value and the second count; and
retrieving the selected threshold from the selected set of thresholds.
14. The method of claim 13 , further comprising performing a look-up operation to retrieve the selected threshold from the selected set of thresholds based on a count of decoding clock cycles of the bit-flipping decoder.
15. The method of claim 12 , further comprising:
selecting a first set of thresholds, a second set of thresholds, a third set of thresholds, or a fourth set of thresholds based on the value of the variable node and based on a reliability indicator associated with the value of the variable node,
wherein:
the first set of thresholds and the third set of thresholds are associated with the first logical value, and
the second set of thresholds and the fourth set of thresholds are associated with the second logical value; and
retrieving the selected threshold from the selected set of thresholds.
16. The method of claim 15 , wherein:
the first set of thresholds and the second set of thresholds are further associated with a first reliability value; and
the third set of thresholds and the fourth set of thresholds are further associated with a second reliability value.
17. The method of claim 16 , wherein:
the first set of thresholds is selected based further on a first bit error rate associated with bits having the first logical value and the first reliability value;
the second set of thresholds is selected based further on a second bit error rate associated with bits having the second logical value and the first reliability value;
the third set of thresholds is selected based further on a third bit error rate associated with bits having the first logical value and the second reliability value; and
the fourth set of thresholds is selected based further on a fourth bit error rate associated with bits having the second logical value and the second reliability value.
18. An apparatus comprising:
means for selecting a first threshold in response to a value of a variable node indicating a first logical value and for selecting a second threshold in response to the value of the variable node indicating a second logical value; and
means for adjusting the value of the variable node in response to a number of unsatisfied check nodes associated with the variable node satisfying the selected threshold.
19. The apparatus of claim 18 , further comprising:
means for storing a representation of a codeword; and
means for performing a bit-flipping decoding operation on the representation of the codeword read from the means for storing, the means for performing the bit-flipping decoding operation comprising:
the means for selecting; and
the means for adjusting.
20. The apparatus of claim 19 , further comprising means for determining a number of unsatisfied check nodes associated with each variable node of a plurality of variable nodes, the plurality of variable nodes corresponding to bits of the representation of the codeword.