IP Library Granted Patent US 11,372,754
Granted Patent B2
US 11,372,754 · App. 16/899,958 · Granted Jun 28, 2022

Storage system and method for enabling a software-defined dynamic storage response

Inventor: Ramanathan Muthiah (Karnataka, IN)
Assignee: Western Digital Technologies, Inc.
G06F12/0246G06F9/30047G06F11/3037G06F12/0292G06F12/0815G11C11/4085G06F2212/7201
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Quick Facts
Patent No.
US 11,372,754
App. No.
16/899,958
Granted
Jun 28, 2022
Kind
B2
Abstract

A storage system and method for enabling a software-defined dynamic storage response are provided. In one embodiment, a controller of a storage system is configured to receive an expected response time from a host; in response to receiving the expected response time from the host, cache a logical-to-physical address table entry of a wordline; and store the cached logical-to-physical address table entry of the wordline as metadata in a next wordline along with host data. Other embodiments are provided.

Claims (33)

1. A method comprising:

performing the following in a storage system comprising a memory:

receiving an expected response time from a host;

in response to receiving the expected response time from the host, caching a logical-to-physical address table entry of a wordline; and

storing the cached logical-to-physical address table entry of the wordline as metadata in a next wordline along with host data.

2. The method of claim 1 , wherein the expected response time is less than an initialization time of the storage system.

3. The method of claim 1 , wherein the cached logical-to-physical address table entry is stored as a header.

4. The method of claim 1 , further comprising altering a frequency of a flush in the storage system to ensure the expected response time is met.

5. The method of claim 4 , wherein the flush comprises an initialization overhead flush.

6. The method of claim 4 , wherein the flush comprises a master table flush.

7. The method of claim 4 , wherein the flush comprises a built parity flush.

8. The method of claim 4 , further comprising altering the frequency of the flush based on one or more of the following: memory block type, number of open memory blocks, and health of a memory block.

9. The method of claim 1 , wherein the memory comprises a three-dimensional memory.

10. A storage system comprising:

a memory; and

a controller configured to:

receive an expected response time from a host;

in response to receiving the expected response time from the host, cache a logical-to-physical address table entry of a wordline; and

store the cached logical-to-physical address table entry of the wordline as metadata in a next wordline along with host data.

11. The storage system of claim 10 , wherein the expected response time is less than an initialization time of the storage system.

12. The storage system of claim 10 , wherein the cached logical-to-physical address table entry is stored as a header.

13. The storage system of claim 10 , wherein the controller is further configured to alter a frequency of a flush in the storage system to ensure the expected response time is met.

14. The storage system of claim 13 , wherein the flush comprises an initialization overhead flush.

15. The storage system of claim 13 , wherein the controller is further configured to alter the frequency of the flush based on memory block type.

16. The storage system of claim 13 , wherein the flush comprises a master table flush.

17. The storage system of claim 13 , wherein the flush comprises a built parity flush.

18. The storage system of claim 13 , wherein the controller is further configured to alter the frequency of the flush based on number of open memory blocks and/or health of a memory block.

19. The storage system of claim 10 , wherein the memory comprises a three-dimensional memory.

20. A storage system comprising:

a memory;

means for receiving an expected response time from a host;

means for caching, in response to receiving the expected response time from the host, a logical-to-physical address table entry of a wordline; and

means for storing the cached logical-to-physical address table entry of the wordline as metadata in a next wordline along with host data.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2020
From: MUTHIAH, RAMANATHAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052926/0807 →
Continuity (1)
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