IP Library Granted Patent US 11,581,305
Granted Patent B2
US 11,581,305 · App. 17/326,231 · Granted Feb 14, 2023

High voltage protection for high-speed data interface

Inventors: Nitin Gupta (Bangalore, IN); Ramakrishnan Subramanian (Bangalore, IN); Sitaram Banda (Vijayawada, IN)
Assignee: Western Digital Technologies, Inc.
H01L27/0288G11C8/08G11C16/26G11C16/30H01L23/60H01L27/0255H01L28/20H01L29/861
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Quick Facts
Patent No.
US 11,581,305
App. No.
17/326,231
Granted
Feb 14, 2023
Kind
B2
Abstract

Various apparatuses, systems, methods, and media are disclosed to provide over-voltage protection to a data interface of a multi-protocol memory card that includes a first communication interface and a second communication interface that enable communication using different protocols. An interface voltage protection circuit includes a control circuit configured to receive a first supply voltage for operating the first communication interface. The interface voltage protection circuit further includes a pull-down circuit operatively connected with the control circuit, configured to pull down a voltage at a supply voltage rail of the second communication interface such that a voltage at a plurality of connector terminals of the second communication interface is lower than the first supply voltage.

Claims (41)

1. A data storage apparatus comprising:

a non-volatile memory (NVM); and

an interface protection circuit for protecting an input-output circuit of the NVM, the interface protection circuit comprising:

a control circuit configured to receive a first supply voltage and to generate a control signal; and

a pull-down circuit configured to control, responsive to the control signal, a supply voltage rail of the input-output circuit such that a voltage at a plurality of outputs of the input-output circuit is higher than a voltage at the supply voltage rail and lower than the first supply voltage.

2. The data storage apparatus of claim 1 , wherein the pull-down circuit comprises a switch connected between the supply voltage rail and a ground reference.

3. The data storage apparatus of claim 2 , wherein the control circuit is further configured to turn on the switch to pull down the voltage at the supply voltage rail to a level lower than the first supply voltage.

4. The data storage apparatus of claim 3 , wherein the control circuit is further configured to pull up a voltage at a control terminal of the switch to the first supply voltage and thereby turn on the switch.

5. The data storage apparatus of claim 1 , wherein the control circuit comprises:

a resistor configured to receive the first supply voltage; and

at least one switch in series with the resistor connected between the first supply voltage and a ground reference,

wherein the resistor and the at least one switch are configured to activate the pull-down circuit responsive to a mode signal in a first state and to deactivate the pull-down circuit responsive to the mode signal in a second state.

6. The data storage apparatus of claim 5 , wherein the pull-down circuit is further configured to, responsive to being activated, pull down the voltage at the supply voltage rail to the ground reference.

7. The data storage apparatus of claim 5 , wherein the control circuit is further configured to generate the mode signal based on a second supply voltage that is lower than the first supply voltage.

8. The data storage apparatus of claim 5 , wherein the at least one switch comprises a first switch and a second switch connected in series, the first switch and the second switch configured to be controlled by the mode signal.

9. The data storage apparatus of claim 8 , wherein:

the first switch comprises an N-type transistor; and

the second switch comprises a P-type transistor.

10. The data storage apparatus of claim 1 , wherein the control circuit is further configured to receive the first supply voltage from a host external to the data storage apparatus.

11. A method of operating an interface protection circuit of a data storage apparatus comprising a non-volatile memory (NVM), the method comprising:

receiving a first supply voltage and a mode signal; and

controlling a supply voltage rail of an input-output circuit of the NVM based on the first supply voltage and the mode signal, such that a voltage at a plurality of outputs of the input-output circuit is higher than a voltage at the supply voltage rail and lower than the first supply voltage.

12. The method of claim 11 , wherein the controlling the supply voltage rail comprises controlling a first switch connected between the supply voltage rail and a ground reference.

13. The method of claim 12 , wherein the controlling the first switch comprises turning on the first switch to pull down the voltage at the supply voltage rail to a level lower than the first supply voltage.

14. The method of claim 13 , wherein the controlling the supply voltage rail comprises controlling, responsive to the mode signal, a second switch to turn on the first switch, the second switch connected between the first supply voltage and the ground reference.

15. The method of claim 11 , wherein the controlling the supply voltage rail comprises:

activating, responsive to the mode signal in a first state, a pull-down circuit connected between the supply voltage rail and a ground reference; and

deactivating, responsive to the mode signal in a second state, the pull-down circuit.

16. The method of claim 15 , wherein the activating the pull-down circuit comprises pulling down the voltage at the supply voltage rail, responsive to the mode signal in a first state, to the ground reference.

17. The method of claim 15 , further comprising:

generating the mode signal based on a second supply voltage that is lower than the first supply voltage.

18. The method of claim 15 , further comprising:

receiving the first supply voltage from a host external to the data storage apparatus.

19. An interface protection circuit for a data storage apparatus, the interface protection circuit comprising:

a first switch configured to output a control signal based on a mode signal and a supply voltage; and

a second switch configured to control, responsive to the control signal, a supply voltage rail of an input-output circuit of the data storage apparatus such that a voltage at a plurality of connector terminals of the input-output circuit is higher than a voltage at the supply voltage rail and lower than the supply voltage.

20. The interface protection circuit of claim 19 , wherein the supply voltage exceeds a voltage tolerance level of the input-output circuit.

21. The interface protection circuit of claim 20 , wherein the second switch is further configured to pull down the voltage at the supply voltage rail responsive to the supply voltage exceeding the voltage tolerance level.

22. An interface protection circuit of a data storage apparatus comprising a non-volatile memory (NVM), the interface protection circuit comprising:

means for receiving a first supply voltage and a mode signal; and

means for controlling a supply voltage rail of an input-output circuit of the NVM based on the first supply voltage and the mode signal, such that a voltage at a plurality of outputs of the input-output circuit is higher than a voltage at the supply voltage rail and lower than the first supply voltage.

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 057651 FRAME 0296 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058981/0958 →
SECURITY INTEREST Recorded Sep 17, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 057651/0296 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2021
From: GUPTA, NITIN; SUBRAMANIAN, RAMAKRISHNAN; BANDA, SITARAM
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 056307/0894 →