IP Library Granted Patent US 11,626,183
Granted Patent B2
US 11,626,183 · App. 17/397,245 · Granted Apr 11, 2023

Method and storage system with a non-volatile bad block read cache using partial blocks

Inventors: Kalpit Bordia (Karnataka, IN); Gautam Dusija (Burlingame, CA)
Assignee: Western Digital Technologies, Inc.
G11C29/42G11C16/3495G11C29/4401G11C29/765
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Quick Facts
Patent No.
US 11,626,183
App. No.
17/397,245
Granted
Apr 11, 2023
Kind
B2
Abstract

A storage system has a memory with a multi-level cell (MLC) block and a partially-bad single-level cell (SLC) block. The storage system repurposes the partially-bad SLC block as a non-volatile read cache for data stored in the MLC block (e.g., cold data that is read relatively frequently) to improve performance of host reads. Because the original version of the data is still stored in the MLC block, the original version of the data can be read if there is an error in the copy of the data stored in the partially-bad SLC block, thus avoiding the need for extensive error-correction handling to account for the poor reliability of the partially-bad SLC block.

Claims (40)

1. A storage system comprising:

a memory comprising a multi-level cell (MLC) block and a partially-bad single-level cell (SLC) block; and

a controller configured to:

copy data stored in the MLC block into the partially-bad SLC block, wherein the data is stored both in the MLC block and the partially-bad SLC block;

receive a request from a host to read the data; and

read the data from the partially-bad SLC block instead of the MLC blocks;

determine if an error exists in the data read from the partially-bad SLC block;

in response to determining that an error does not exist in the data read from the partially-bad SLC block, return the data read from the partially-bad SLC block to the host and

in response to determining that an error exists in the data read from the partially-bad SLC block, read the data from the MLC block and return the data read from the MLC block to the host.

2. The storage system of claim 1 , wherein the controller is further configured to create a mapping between the MLC block and the partially-bad SLC block, so that the data is read from the partially-bad SLC block instead of the MLC block in response to receiving the request from the host.

3. The storage system of claim 2 , wherein the controller is further configured to clear the mapping between the MLC block and the partially-bad SLC block in response to determining that an error exists in the data read from the partially-bad SLC block.

4. The storage system of claim 1 , wherein the controller is further configured to copy the data stored in the MLC block into the partially-bad SLC block in response to information received from the host.

5. The storage system of claim 1 , wherein the controller is further configured to determine that the data stored in the MLC block should be copied to the partially-bad SLC block by identifying the data as cold data that was read more than a threshold number of times.

6. The storage system of claim 1 , wherein the controller is further configured to copy the data as a background operation.

7. The storage system of claim 1 , wherein the controller is further configured to copy the data in response to determining that a program-erase count of the partially-bad SLC block is below a threshold.

8. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

9. In a storage system comprising a memory comprising a multi-level cell (MLC) block and a partially-bad single-level cell (SLC) block configured for use as a read cache, a method comprising:

identifying data stored in the MLC block to be copied into the read cache;

storing a copy of the data in the read cache;

receiving a request from a host to read the data;

in response to the request, reading the copy of the data from the read cache;

performing an error check on the copy of the data read from the read cache; and

in response to the copy of the data read from the read cache passing the error check, returning the copy of the data to the host.

10. The method of claim 9 , wherein identifying the data comprises determining that the data is cold data but is associated with a read counter having a count above a threshold value.

11. The method of claim 9 , wherein identifying the data comprises determining that a read threshold on the MLC block has been exceeded without an overwrite to the MLC block.

12. The method of claim 9 , wherein the data is identified based on a host communication.

13. The method of claim 9 , further comprising:

in response to the copy of the data read from the read cache failing the error check, reading the data from the MLC block and returning the data read from the MLC block to the host.

14. The method of claim 13 , further comprising:

in response to the copy of the data read from the read cache failing the error check, removing a mapping between the MLC block and the read cache.

15. The method of claim 9 , wherein the copy of the data is stored as a background operation.

16. The method of claim 9 , wherein the copy of the data is stored in response to a determination that the read cache has capacity to store the copy of the data.

17. The method of claim 9 , wherein the copy of the data is stored in response to a determination that a program-erase count (PEC) of the read cache is below a threshold.

18. A storage system comprising:

a memory comprising a multi-level cell (MLC) block and a partially-bad single-level cell (SLC) block;

means for copying data stored in the MLC block into the partially-bad SLC block, wherein the data is stored both in the MLC block and the partially-bad SLC block;

means for receiving a request from a host to read the data; and

means for reading the data from the partially-bad SLC block instead of the MLC block;

means for performing an error check on the copy of the data read from the read cache; and

means for returning the copy of the data to the host in response to the copy of the data read from the read cache passing the error check.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 058426 FRAME 0815 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058965/0679 →
SECURITY INTEREST Recorded Dec 9, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 058426/0815 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 9, 2021
From: BORDIA, KALPIT; DUSIJA, GAUTAM
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 057122/0821 →