IP Library Granted Patent US 10,733,100
Granted Patent B2
US 10,733,100 · App. 16/003,914 · Granted Aug 4, 2020

Method and apparatus for classifying and buffering write commands

Inventor: Shay Benisty (Beer Sheva, IL)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F12/0815G06F3/061G06F3/0656G06F3/0679G06F12/0804G06F12/0855G06F12/0868G06F12/0871G06F2212/1024G06F2212/1032G06F2212/1056G06F2212/214G06F2212/312G06F2212/7203
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,733,100
App. No.
16/003,914
Granted
Aug 4, 2020
Kind
B2
Abstract

Embodiments of the present disclosure generally relate to a target device handling overlap write commands. In one embodiment, a target device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes a random accumulated buffer, a sequential accumulated buffer, and an overlap accumulated buffer. The controller is configured to receive a new write command, classify the new write command, and write data associated with the new write command to one of the random accumulated buffer, the sequential accumulated buffer, or the overlap accumulated buffer. Once the overlap accumulated buffer becomes available, the controller first flushes to the non-volatile memory the data in the random accumulated buffer and the sequential accumulated buffer that was received prior in sequence to the data in the overlap accumulated buffer. The controller then flushes the available overlap accumulated buffer, ensuring that new write commands override prior write commands.

Claims (44)

1. A data storage device, comprising:

a non-volatile memory; and

a controller coupled to the non-volatile memory, the controller comprising a random accumulated buffer, a sequential accumulated buffer, and an overlap accumulated buffer, the controller configured to:

receive a new write command;

classify the new write command; and

write data associated with the new write command to one of the random accumulated buffer, the sequential accumulated buffer, or the overlap accumulated buffer based on the classification of the new write command.

2. The data storage device of claim 1 , wherein the controller further comprises a command parser.

3. The data storage device of claim 1 , wherein the controller further comprises a write command accelerator.

4. The data storage device of claim 1 , wherein the controller is further configured to detect a cache collision of the new write command.

5. The data storage device of claim 4 , wherein the new write command is classified as an overlap write command when a cache collision is detected.

6. The data storage device of claim 1 , wherein the random accumulated buffer stores one or more write commands classified as random, the sequential accumulated buffer stores one or more write commands classified as sequential, and the overlap accumulated buffer stores one or more write commands classified as overlap.

7. A data storage device, comprising:

a non-volatile memory; and

a controller coupled to the non-volatile memory, the controller comprising a random accumulated buffer, a sequential accumulated buffer, and an overlap accumulated buffer, the controller configured to:

fetch one or more commands;

parse and detect each of the one or more commands as a write command, a read command, or an erase command;

classify each of the one or more commands; and

write data associated with each of the one or more commands to one of the random accumulated buffer, the sequential accumulated buffer, or the overlap accumulated buffer based on the classification of each of the one or more commands.

8. The data storage device of claim 7 , wherein the controller is further configured to detect a cache collision of a first command of the one or more commands.

9. The data storage device of claim 8 , wherein the controller is further configured to classify the first command as an overlap write command.

10. The data storage device of claim 9 , wherein the controller is further configured to write data associated with the overlap write command to the overlap accumulated buffer.

11. The data storage device of claim 8 , wherein a collision table is used to detect the cache collision.

12. The data storage device of claim 7 , wherein the controller is further configured to classify a second command of the one or more commands as a random write command.

13. The data storage device of claim 12 , wherein the controller is further configured to write data associated with the random write command to the random accumulated buffer.

14. The data storage device of claim 7 , wherein the controller is further configured to classify a second command of the one or more commands as a sequential write command.

15. The data storage device of claim 14 , wherein the controller is further configured to write data associated with the sequential write command to the sequential accumulated buffer.

16. The data storage device of claim 7 , wherein the controller further comprises a cache and a command parser.

17. A data storage device, comprising:

a non-volatile memory; and

a controller coupled to the non-volatile memory, the controller comprising a random accumulated buffer, a sequential accumulated buffer, and an overlap accumulated buffer, the controller configured to:

receive a plurality of commands;

parse and detect each of the plurality of commands as a write command, a read command, or an erase command;

determine one or more commands of the plurality of commands are write commands;

classify each of the one or more write commands as overlap write commands, random write commands, or sequential write commands;

write data associated with each of the one or more write commands to one of the random accumulated buffer, the sequential accumulated buffer, or the overlap accumulated buffer based on the classification of each of the one or more write commands; and

post a command completion message.

18. The data storage device of claim 17 , wherein a command is classified as an overlap command when a cache collision is detected.

19. The data storage device of claim 17 , wherein the controller further comprises a command parser.

20. The data storage device of claim 19 , wherein the command parser is configured to:

parse and detect each of the plurality of commands; and

classify the one or more write commands as random write commands and sequential write commands.

21. The data storage device of claim 17 , wherein the random accumulated buffer stores data associated with write commands classified as random, the sequential accumulated buffer stores data associated with write commands classified as sequential, and the overlap accumulated buffer stores data associated with write commands classified as overlap.

22. The data storage device of claim 17 , wherein the controller further comprises a cache.

23. The data storage device of claim 22 , wherein the cache comprises the random accumulated buffer, the sequential accumulated buffer, and the overlap accumulated buffer.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2018
From: BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046823/0667 →
Continuity (2)
Provisional Application 62518260 · Jun 12, 2017
Related Publication 20180357170A1 · Dec 13, 2018
Cited By (1)
US 12,417,180