Dynamic bitscan for non-volatile memory
Technology is disclosed herein for a dynamic bitscan. The dynamic bitscan may include performing a first bitscan of a first strict subset of memory cells. Then, based on results of the first bitscan, a determination is made whether to perform a second bitscan of a second strict subset of memory cells. Prior to the bitscan(s) a verify reference voltage may be applied to both strict subsets of memory cells. Skipping the second bitscan saves considerable time. However, the second bitscan is performed at least sometimes, which increases accuracy. The first strict subset of memory cells and the second strict subset of memory cells may have different locations relative to some point in the block that contains the memory cells. The first strict subset of memory cells and the second strict subset may have different programming speeds.
1. An apparatus, comprising:
one or more control circuits configured to connect to a three-dimensional memory structure comprising blocks of memory cells, wherein the one or more control circuits are configured to:
apply one or more verify reference voltages to a group of memory cells in a selected block in the three-dimensional memory structure;
perform a first bitscan of a first strict subset of the group of memory cells that have a first programming speed, the first bitscan comprising a first count of first sensing results from applying the one or more verify reference voltages to the first strict subset of the group; and
perform a second bitscan of a second strict subset of the group of memory cells that have a second programming speed responsive to the first count meeting a criterion, wherein the second bitscan is not performed if the criterion is not met, the second bitscan comprising a second count of second sensing results from applying the one or more verify reference voltages to the second strict subset of the group.
2. The apparatus of claim 1 , wherein the one or more control circuits are further configured to:
select the first strict subset for the first bitscan and the second strict subset for the second bitscan based on which strict subset programs faster and which strict subset programs slower.
3. The apparatus of claim 1 , wherein the one or more control circuits are further configured to:
select slower programming group for the first strict subset for the first bitscan and faster programming group for the second strict subset for the second bitscan; and
determine whether program verify has passed based on the first count and further on the second count when the second bitscan is performed.
4. The apparatus of claim 3 , wherein the one or more control circuits are further configured to:
determine a fail bit count based on the first count, wherein a particular memory cell is counted as a fail bit if its threshold voltage (Vt) is below the verify reference voltage associated with a data state to which the particular memory cell is being programmed; and
perform the second bitscan responsive to the fail bit count being less than allowed.
5. The apparatus of claim 1 , wherein:
the first count is of how many memory cells in the first strict subset have a threshold voltage (Vt) above a first verify reference voltage for a data state Sn;
the one or more control circuits are further configured to:
select a faster programming group for the first strict subset for the first bitscan and a slower programming group for the second strict subset for the second bitscan; and
determine, based on the first count and further on the second count when the second bitscan is performed, whether to initiate verify in a next program loop for a data state Sn+1 having a second verify reference voltage that is greater than the first verify reference voltage.
6. The apparatus of claim 5 , wherein the one or more control circuits are further configured to perform the second bitscan responsive to the first bit count being less than a threshold for initiating verify for data state Sn+1.
7. The apparatus of claim 1 , wherein:
one of the first strict subset and the second strict subset are inner memory holes; and
the other of the first strict subset and the second strict subset are outer memory holes.
8. The apparatus of claim 1 , wherein:
the first strict subset and the second strict subset are different distances from an edge of the selected block in a bit line direction.
9. The apparatus of claim 1 , wherein:
the first strict subset of memory cells comprises a first group of one or more bits in each of a plurality of bytes of memory cells, wherein each byte of memory cells is grouped together physically; and
the second strict subset of memory cells comprises a second group of one or more bits in each of the plurality of bytes of memory cells.
10. The apparatus of claim 1 , wherein:
the one or more control circuits reside on a first semiconductor die; and
the three-dimensional memory structure resides on a first semiconductor die that is attached to the first semiconductor die.
11. A method for operating non-volatile memory, the method comprising:
applying a first verify reference voltage to a word line connected to a group of NAND memory cells that are organized as a plurality of bytes, wherein each byte of memory cells is grouped together physically within a block in a three-dimensional memory structure;
sensing the group of memory cells in response to the first verify reference voltage;
selecting a first strict subset of one or more bits in each of a subset of the plurality of bytes of memory cells;
determining a first count of how many of the memory cells in the first strict subset meet a threshold voltage (Vt) criterion with respect to the first verify reference voltage, the first count being based on the sensing of the first strict subset;
responsive to the first strict subset meeting the criterion with respect to the first verify reference voltage:
selecting a second strict subset of one or more bits in each of the subset of the plurality of bytes of memory cells; and
determining a second count how many of the memory cells in the second strict subset meet the Vt criterion with respect to the first verify reference voltage, the second count being based on the sensing of the second strict subset;
applying a second verify reference voltage to the word line connected to the group of memory cells;
sensing the group of memory cells in response to the second verify reference voltage;
determining a third count of how many of the memory cells in the first strict subset meet a Vt criterion with respect to the second verify reference voltage; and
responsive to the first strict subset not meeting the Vt criterion with respect to the second verify reference voltage: omitting counting of how many of the memory cells in the second strict subset meet the Vt criterion with respect to the second verify reference voltage.
12. The method of claim 11 , further comprising:
selecting the first strict subset of memory cells and the second strict subset of memory cells based on a difference between a first programming speed of the first strict subset and a second programming speed of the second strict subset.
13. The method of claim 11 , further comprising:
selecting the first strict subset of memory cells and the second strict subset of memory cells based on a difference in a first distance of the first strict subset from an edge of the block in a bitline direction and a second distance of the second strict subset from the edge of the block.
14. The method of claim 11 , further comprising:
selecting a slower programming group for the first strict subset and a faster programming group for the second strict subset; and
determining whether program verify has passed based on the first count and further on the second count.
15. The method of claim 11 , further comprising:
selecting a faster programming group for the first strict subset and a slower programming group for the second strict subset; and
determining whether to initiate program verify for a first data state having a higher reference voltage than a second data state presently being verified based on the first count and further on the second count.
16. A non-volatile storage system, comprising:
a three-dimensional memory structure comprising blocks of memory cells arranged as NAND strings, the three-dimensional memory structure having bit lines extending over the blocks; and
one or more control circuits in communication with the three-dimensional memory structure, the one or more control circuits configured to:
apply a verify reference voltage to a group of memory cells in a selected block in the three-dimensional memory structure;
perform a first bitscan of a first strict subset of the group of memory cells that each have a first distance in a bit line direction from an edge of the selected block; and
perform a second bitscan of a second strict subset of the group of memory cells that each have a second distance in the bit line direction from the edge of the selected block responsive to a condition being met with respect to the first bitscan, wherein the second bitscan is not performed if the condition is not met.
17. The non-volatile storage system of claim 16 , wherein the one or more control circuits are further configured to:
select the first strict subset for the first bitscan and the second strict subset for the second bitscan based on a first programming speed of the first strict subset and a second programming speed of the second strict subset.
18. The non-volatile storage system of claim 17 , wherein the one or more control circuits are further configured to:
select a slower programming group for the first strict subset for the first bitscan and a faster programming group for the second strict subset for the second bitscan; and
determine whether program verify has passed based on the first bitscan and further on the second bitscan when the second bitscan is performed.
19. The non-volatile storage system of claim 17 , wherein the one or more control circuits are further configured to:
select a faster programming group for the first strict subset for the first bitscan and a slower programming group for the second strict subset for the second bitscan; and
determine, based on the first count and further on the second count when the second bitscan is performed, whether to initiate on a next program loop verify for a data state that is verified with a higher reference voltage than the verify reference voltage that was applied to the group.
20. The non-volatile storage system of claim 16 , wherein:
the first strict subset of memory cells comprises a first group of one or more bits in each of a plurality of bytes of memory cells, wherein each byte of memory cells is grouped together physically; and
the second strict subset of memory cells comprises a second group of one or more bits in each of the plurality of bytes of memory cells.