Hierarchical fail bit counting circuit in memory device
Apparatuses and techniques for counting 0 or 1 bits in a set of bits using both serial and parallel processes. The counting process includes a hierarchy in which the count from different parallel processes at one level in the hierarchy are passed to a smaller number of different parallel processes at a lower level in the hierarchy. A final count is obtained by an accumulator below the lowest level of the hierarchy. The position and configuration of the circuits can be set to equalize a number of circuits which process the different bits, so that a maximum delay relative to the accumulator is equalized.
1. An apparatus, comprising:
a plurality of sets of tag circuits, each set of tag circuits is configured to receive input bits and output one or more signals which indicate a number of fail bits, the sets of tag circuits are configured to operate in parallel, and the tag circuits in each set are configured to operate serially;
a plurality of aggregation circuits, the plurality of aggregation circuits comprises first sets of aggregation circuits configured to operate in parallel to receive the signals from the sets of tag circuits, in each of the first sets of aggregation circuits, a last aggregation circuit is configured to output a signal indicating a sum of fail bits for the set; and
an accumulator configured to count the fail bits based on signals output from the plurality of aggregation circuits.
2. The apparatus of claim 1 , wherein:
each aggregation circuit is configured to receive signals which indicate the number of fail bits from multiple sets of tag circuits.
3. The apparatus of claim 1 , wherein:
the plurality of aggregation circuits further comprise second sets of aggregation circuits configured to receive the signals indicating the sums of fails bits from the first sets of aggregation circuits; and
in each of the second sets of aggregation circuits, a last aggregation circuit is configured to output a signal indicating a sum of fail bits for the set.
4. The apparatus of claim 1 , wherein:
each set of aggregation circuits in the first sets of aggregation circuits comprises multiple aggregation circuits which operate serially.
5. The apparatus of claim 3 , wherein:
the second sets of aggregation circuits operate in parallel; and
each set of aggregation circuits in the second sets of aggregation circuits comprises multiple aggregation circuits which operate serially.
6. The apparatus of claim 3 , wherein:
a number of aggregation circuits in the second sets of aggregation circuits is less than a number of aggregation circuits in the first sets of aggregation circuits.
7. The apparatus of claim 1 , wherein:
each set of tag circuits operates according to clock cycles and the signal output by the set of tag circuits indicates the corresponding number of fail bits according to a number of clock cycles in which the signal output by the set of tag circuits is at a specified level.
8. The apparatus of claim 1 , further comprising:
circuits for loading the bits into the plurality of sets of tag circuits in successive cycles, wherein the accumulator is configured to count the fail bits in each cycle.
9. The apparatus of claim 1 , wherein:
the fail bits indicate a number of memory cells in a page of data which have not completed programming to an assigned data state in a program loop of a programming operation.
10. The apparatus of claim 1 , wherein:
the input bits comprises even and odd-numbered groups of bits; and
each set of tag circuits is configured to receive input bits from the even and odd-numbered groups of bits and to provide the one or more signals which indicate the number of fail bits as a signal which indicates a number of fail bits in the even-numbered group of bits and a signal which indicates a number of fail bits in the odd-numbered group of bits.
11. The apparatus of claim 1 , wherein in each set of tag circuits:
each tag circuit comprises a latch into which one of the bits is loaded, a gating device connected to the latch and configured to pass a clock signal when the one of the bits is a pass bit and block the clock signal when the one of the bits is a fail bit, and a set-reset latch configured to enter a set state when the one of the bits is the fail bit and to remain in a reset state when the one of the bits is the pass bit.
12. The apparatus of claim 11 , wherein in each set of tag circuits:
for each tag circuit before a last tag circuit, an output of the set-reset latch is connected to an input of a next tag circuit; and
for the last tag circuit, an output of the set-reset latch is connected to one of the aggregation circuits.