Granted Patent B2

US 9,576,671 · App. 14/549,535 · Granted Feb 21, 2017

Abstract

Claims (57)

1. A machine-implemented method, comprising:

reading a first plurality of memory cells of a flash memory device, wherein the read first plurality of memory cells is associated with an error rate that exceeds an error threshold;

reading a second plurality of memory cells of the flash memory device a plurality of times, each of the reads using a read level voltage adjusted by a respective one of a plurality of read level offset voltages, wherein the second plurality of memory cells is adjacent to the first plurality of memory cells;

determining a plurality of reliability values based on reading the second plurality of memory cells;

identifying an offset voltage, offset from the read level voltage, that corresponds to a zero crossing point in a range of the plurality of reliability values;

setting the read level voltage to a calibrated voltage based on the offset voltage; and

re-reading the first plurality of memory cells using the read level voltage set to the calibrated voltage.

2. The machine-implemented method of claim 1 , further comprising:

storing a plurality of predetermined read level offsets, each predetermined read level offset being associated with a group of wordlines in the flash memory device for use with the read level voltage in reading memory cells in the group of wordlines;

for a respective group of wordlines, updating a read level offset previously stored for the group with the identified offset voltage; and

in connection with a read operation, retrieving the updated read level offset to set the read level voltage to the calibrated voltage, and using the read level voltage set to the calibrated voltage to read the respective group of wordlines.

3. The machine-implemented method of claim 1 , wherein the first plurality of memory cells comprises a first wordline and the second plurality of memory cells comprises a second wordline.

4. The machine-implemented method of claim 1 , wherein the first plurality of memory cells comprises a first codeword and the second plurality of memory cells comprises a second codeword.

5. The machine-implemented method of claim 1 , wherein setting the read level voltage to the calibrated voltage comprises:

adjusting the read level voltage by the identified offset voltage to read memory cells across a plurality of memory channels, wherein each channel is configured to address one or more memory blocks.

6. The machine-implemented method of claim 5 , wherein setting the read level voltage to the calibrated voltage further comprises:

associating the identified offset voltage with all blocks and all pages in the flash memory device that are addressable by the plurality of memory channels so that the read level is adjusted by the identified offset voltage when reading memory cells of any page or block associated with the plurality of memory channels.

7. The machine-implemented method of claim 1 , wherein setting the read level voltage to the calibrated voltage further comprises:

associating the identified offset voltage with a page address; and

adjusting the read level by the identified offset voltage when reading memory cells associated with the page address via any of a plurality of memory channels, each page address addressable via the plurality of memory channels being associated with a different offset voltage.

8. The machine-implemented method of claim 1 , wherein for the plurality of reliability values, a positive reliability value is indicative of a corresponding output state being a binary 0, and a negative reliability value is indicative of the corresponding output state being a binary 1.

9. The machine-implemented method of claim 1 , wherein each generated reliability value is indicative of a likelihood that an output state of the memory cells is equal to one of multiple predetermined programmed states.

10. The machine-implemented method of claim 1 , further comprising:

determining the zero crossing point based on an interpolation of the reliability values.

11. A data storage system, comprising:

a plurality of flash memory devices, each flash memory device comprising a plurality of memory blocks; and

a controller coupled to the plurality of flash memory devices, wherein the controller is configured to:

read a first plurality of memory cells of one or more of the plurality of memory blocks, wherein the read first plurality of memory cells is associated with an error rate that satisfies an error threshold;

read a second plurality of memory cells of one or more of the plurality of memory blocks a plurality of times, each of the reads using a read level voltage adjusted by a respective one or a plurality of read level offset voltages, wherein the second plurality of memory cells is adjacent to the first plurality of memory cells;

determine a plurality of reliability values based on reading the second plurality of memory cells;

identify an offset voltage, offset from the read level voltage, that corresponds to a zero crossing point in a range of the plurality of reliability values

set the read level voltage to a calibrated voltage based on the offset voltage; and

re-read the first plurality of memory cells using the read level voltage set to the calibrated voltage.

12. The data storage system of claim 11 , wherein the controller is further configured to:

store a plurality of predetermined read level offsets, each predetermined read level offset being associated with a group of wordlines for use with the read level voltage in reading memory cells in the group of wordlines;

for a respective group of wordlines, update a read level offset previously stored for the group with the identified offset voltage; and

in connection with a read operation, retrieve the updated read level offset to set the read level voltage to the calibrated voltage, and using the read level voltage set to the calibrated voltage to read the respective group of wordlines.

13. The data storage system of claim 11 , wherein the first plurality of memory cells comprises a first wordline and the second plurality of memory cells comprises a second wordline.

14. The data storage system of claim 11 , wherein the first plurality of memory cells comprises a first codeword and the second plurality of memory cells comprises a second codeword.

15. The data storage system of claim 11 , wherein setting the read level voltage to the calibrated voltage comprises:

adjusting the read level voltage by the identified offset voltage to read memory cells across a plurality of memory channels, wherein each channel is configured to address one or more memory blocks.

16. The data storage system of claim 15 , wherein the controller is further configured to:

associate the identified offset voltage with all blocks and all pages addressable by the plurality of memory channels so that the read level is adjusted by the identified offset voltage when reading memory cells of any page or block associated with the plurality of memory channels.

17. The data storage system of claim 11 , wherein the controller is further configured to:

associating the identified offset voltage with a page address; and

adjusting the read level by the identified offset voltage when reading memory cells associated with the page address via any of a plurality of memory channels, each page address addressable via the plurality of memory channels being associated with a different offset voltage.

18. A machine-implemented method, comprising:

reading a first plurality of memory cells of a flash memory device, wherein the read first plurality of memory cells generates an error rate exceeding an error threshold;

reading a second plurality of memory cells adjacent to the first plurality of memory cells a plurality of times to generate a plurality of reliability values, each of the reads using a read level adjusted by a respective one or a plurality of read level offsets;

identifying an offset from the read level that corresponds to a zero crossing point in a range of the plurality of reliability values;

adjusting the read level based on the offset; and

re-reading the first plurality of memory cells using the adjusted read level.

19. The machine-implemented method of claim 18 , further comprising:

storing a plurality of predetermined read level offsets, each predetermined read level offset being associated with a group of wordlines in the flash memory device and for use with the read level in reading memory cells in the group of wordlines;

for a respective group of wordlines, updating a read level offset previously stored for the group with the identified offset; and

in connection with a read operation, retrieving the updated read level offset to adjust the read level, and using the adjusted read level to read the respective group of wordlines.

20. The machine-implemented method of claim 18 , wherein the first plurality of memory cells comprises a first codeword or a first wordline and the second plurality of memory cells comprises a second codeword or a second wordline.

Assignments (11)