Low power state staging
The present disclosure generally relates to split, non-operational power states for a data storage device. The data storage device can transition between the split, non-operational power states without advertising the transition to the host device. The power state parameters that are advertised to the host device are adjusted such that the host device is guided to the correct power decision based on the advertised power and duration. By splitting the non-operational power states, the data storage device does not incur additional transitional energy costs for short idle durations.
1. A data storage device, comprising:
at least one non-volatile memory device;
at least one volatile memory device;
a timer; and
a controller coupled to the timer, the at least one non-volatile memory device, and the at least one volatile memory device, the controller configured to:
receive a request from a host device to enter into the lowest power state advertised to the host device;
after a predetermined period of time, flush data from the at least one volatile memory device to the at least one non-volatile memory device, wherein the predetermined period of time is greater than 0.1 seconds; and
cause the data storage device to enter the lowest power state advertised to the host device, wherein the controller is further configured not to advertise the predetermined period of time to the host device.
2. The data storage device of claim 1 , wherein the predetermined period of time is greater than 1 second.
3. The data storage device of claim 1 , wherein the predetermined period of time is between 1 second and 10 seconds.
4. The data storage device of claim 1 , wherein after receiving the request and prior to completion of the predetermined period of time, the at least one volatile memory device is configured to remain in retention mode.
5. The data storage device of claim 1 , wherein the at least one volatile memory device comprises SRAM.
6. The data storage device of claim 1 , wherein the at least one non-volatile memory device comprises NAND.
7. A data storage device, comprising:
at least one non-volatile memory device;
at least one volatile memory device;
a timer; and
a controller coupled to the timer, the at least one non-volatile memory device, and the at least one volatile memory device, the controller configured to:
receive a request from a host device to enter into the lowest power state advertised to the host device;
after a predetermined period of time, flush data from the at least one volatile memory device to the at least one non-volatile memory device, wherein the predetermined period of time is greater than 0.1 seconds; and
cause the data storage device to enter the lowest power state advertised to the host device, wherein the controller is further configured to reduce power to systems other than the at least one volatile memory device upon receiving the request.
8. That data storage device of claim 7 , wherein the controller is further configured to cause the data storage device to enter the lowest power state advertised to the host device after the predetermined period of time.
9. A data storage device, comprising:
at least one non-volatile memory device;
at least one volatile memory device;
a timer; and
a controller coupled to the timer and the at least one non-volatile memory device, the controller configured to:
present a power state descriptor table to a host device;
receive a request from the host device to enter into a lowest power state presented to the host device;
after a predetermined period of time, flush data from the at least one volatile memory device to the at least one non-volatile memory device, wherein the predetermined period of time is greater than 0.1 seconds;
cause the data storage device to enter the lowest power state advertised to the host device after the predetermined period of time; and
dynamically change the power state description table.
10. The data storage device of claim 9 , wherein the controller is further configured to increase a maximum power.
11. The data storage device of claim 10 , wherein idle power is unchanged while the controller increases the maximum power.
12. The data storage device of claim 9 , wherein a maximum power exceeds an advertised power limit presented to the host device.
13. The data storage device of claim 12 , wherein the maximum power is substantially equivalent to a transitional energy needed to transition between different states.
14. The data storage device of claim 9 , wherein dynamically changing the power state description table is not advertised to the host device.
15. A data storage device, comprising:
non-volatile memory means;
volatile memory means; and
a controller coupled to the volatile memory means and the non-volatile memory means, wherein the controller is configured to:
extend latency advertised to a host device;
receive a request from the host device to enter into a lowest power state presented to the host device;
after a predetermined period of time, flush data from the volatile memory means to the non-volatile memory means, wherein the predetermined period of time is greater than 0.1 seconds; and
enter into the lowest power state advertised to the host device after the predetermined period of time.
16. The data storage device of claim 15 , wherein extending latency advertised to the host device comprises adding 100 ms to 400 ms to the latency advertised to the host device.
17. The data storage device of claim 15 , further comprising a timer.
18. The data storage device of claim 17 , wherein the controller is further configured to set the timer to the predetermined period of time.
19. The data storage device of claim 15 , wherein the controller is further configured to calculate latency.
20. The data storage device of claim 15 , wherein the lowest advertised power state is a non-operational power state.