System and method for lower page data recovery in a solid state drive
View Patent ↗In some embodiments of the present invention, a data storage system includes a controller and a non-volatile memory array having a plurality of memory pages. The controller performs a method that efficiently resolves the lower page corruption problem. In one embodiment, the method selects programmed lower page(s) for which paired upper page(s) have not been programmed, reads data from those selected lower page(s), corrects the read data, and reprograms the read data into those lower page(s). Since the number of lower pages in this condition is typically low (e.g., several pages in a block with hundreds or thousands of pages), this is a much more efficient method than reprogramming the entire block. In another embodiment, a similar reprogramming method is applied as a data recovery scheme in situations in which only lower pages are programmed (e.g., SLC memory, MLC memory in SLC mode, etc.).
1. A solid-state storage system, including:
a non-volatile memory array including a plurality of memory blocks, each memory block including lower memory pages paired with upper memory pages; and
a controller configured to:
select, from the memory blocks, a programmed lower memory page that has a paired upper memory page that has not been programmed;
read first data from the selected lower memory page, wherein at least a portion of the read first data is corrupted;
apply error correction to the read first data to generate corrected first data; and
program the corrected first data to the selected lower memory page.
2. The solid-state storage system of claim 1 , wherein the non-volatile memory array comprises multi-level memory (MLC) cells.
3. The solid-state storage system of claim 1 , wherein the controller is configured to select the programmed lower memory page from an open memory block of the memory blocks.
4. The solid-state storage system of claim 3 , wherein the open memory block comprises a block on which programming was initiated but not completed when the storage system was last shut down.
5. The solid-state storage system of claim 1 , wherein the controller is further configured to:
select, from a memory block associated with the selected lower memory page, at least one other lower memory page which has a paired upper memory page that has not been programmed;
read second data from the selected at least one other lower memory page;
apply error correction to the read second data to generate corrected second data; and
program the corrected second data to the selected at least one other lower memory page.
6. The solid-state storage system of claim 5 , wherein the controller is further configured to:
select, from the memory block, each lower memory page which has a paired upper memory page that has not been programmed; and
reprogram data to each of the selected lower memory pages.
7. The solid-state storage system of claim 1 , wherein the controller is configured to program the corrected first data to the selected lower memory page as part of a startup sequence.
8. The solid-state storage system of claim 1 , wherein the error correction comprises at least one of low density parity check (LDPC) and RAID recovery.
9. The solid-state storage system of claim 1 , wherein the controller is configured to use at least one of metadata and scanning to select the programmed lower memory page.
10. A method of preserving data integrity in a solid-state storage system that includes a non-volatile memory array including a plurality of memory blocks, each including a plurality of memory pages, the method including:
selecting, from the memory blocks, a programmed lower memory page that has a paired upper memory page that has not been programmed;
reading first data from the selected lower memory page, wherein at least a portion of the read first data is corrupted;
applying error correction to the read first data to generate corrected first data; and
programming the corrected first data to the selected lower memory page.
11. The method of claim 10 , wherein the non-volatile memory array comprises multi-level memory (MLC) cells.
12. The method of claim 10 , wherein selecting comprises selecting the programmed lower memory page from an open memory block of the memory blocks.
13. The method of claim 12 , wherein the open memory block comprises a block on which programming was initiated but not completed when the storage system was last shut down.
14. The method of claim 10 , further comprising:
selecting, from a memory block associated with the selected lower memory page, at least one other lower memory page which has a paired upper memory page that has not been programmed;
reading second data from the selected at least one other lower memory page;
applying error correction to the read second data to generate corrected second data; and
programming the corrected second data to the selected at least one other lower memory page.
15. The method of claim 14 , further comprising:
selecting, from the memory block, each lower memory page which has a paired upper memory page that has not been programmed; and
reprogramming data to each of the selected lower memory pages.
16. The method of claim 10 , wherein programming the corrected first data to the selected lower memory page is performed as part of a startup sequence.
17. The method of claim 10 , wherein the error correction comprises at least one of low density parity check (LDPC) and RAID recovery.
18. The method of claim 10 , wherein selecting the programmed lower memory page comprises using at least one of metadata and scanning.