Granted Patent B2

US 12,436,686 · App. 18/390,296 · Granted Oct 7, 2025

Inventors: Yichen Wang (Shanghai, CN); Ming Wang (Shanghai, CN); Anubhav Khandelwal (San Jose, CA); Liang Li (Shanghai, CN)

Assignee: Sandisk Technologies, Inc.

G06F3/0619G06F3/0655G06F3/0679

Abstract

Claims (50)

1. A memory device, comprising:

a memory block including an array of memory cells that are arranged in a plurality of word lines an in a plurality of NAND strings, the plurality of NAND strings being divided into a plurality of string groups; and

control circuitry configured to:

in a first string group of the plurality of string groups, perform a broad voltage level range bit error rate estimation scan to identify an approximate optimal read reference voltage for the first string group;

in the first string group, perform a narrow voltage level range bit error rate estimation scan, using the approximate optimal read reference voltage, to determine an optimal read reference voltage for the first string group; and

in a second string group of the plurality of string groups, without performing the broad voltage level range bit error rate estimate scan, perform the narrow voltage level range bit error rate estimation scan, using the approximate optimal read reference voltage for the first string group, to determine an optimal read reference voltage for the second string group,

wherein the broad voltage level range bit error rate estimation scan includes scanning a broader range of voltage levels than the narrow voltage level range bit error rate estimation scan.

2. The memory device of claim 1 , wherein the approximate optimal read reference voltage for the first string group and the optimal read reference voltage for the first string group are determined by scanning the memory cells of a first word line and the first string group.

3. The memory device of claim 2 , wherein the optimal read reference voltage for the second string group is determined by scanning the memory cells of the first word line and the second string group.

4. The memory device of claim 1 , the control circuitry further configured to:

in the first string group, perform the broad voltage level range bit error rate estimation scan to identify an approximate optimal read reference voltage for the memory cells of a second word line and the first string group; and

in the first string group, perform the narrow voltage level range bit error rate estimation scan, using the optimal read reference voltage for the second word line and the first string group, to determine an optimal read reference voltage for the second word line and the first string group.

5. The memory device of claim 4 , the control circuitry further configured to:

in the second string group, perform the narrow voltage level range bit error rate estimation scan for the memory cells of a second word line and the second string group, using the approximate optimal read reference voltage for the second word line and the first string group, to determine an optimal read reference voltage for the second word line and the second string group.

6. The memory device of claim 1 , the control circuitry further configured to:

setting an optimal read reference voltage for a third string group adjacent to the second string group to the optimal read reference voltage for the second string group.

7. The memory device of claim 3 , the control circuitry further configured to:

setting an optimal read reference voltage for a second word line adjacent to the first word line to the optimal read reference voltage for the first word line and the second string group.

8. A method of operating a non-volatile semiconductor memory device, the method comprising the steps of:

preparing a memory block that includes an array of memory cells that are arranged in a plurality of word lines and in a plurality of NAND strings, the plurality of NAND strings being divided into a plurality of string groups;

in a first string group of the plurality of string groups, performing a broad voltage level range bit error rate estimation scan to identify an approximate optimal read reference voltage for the first string group;

in the first string group, performing a narrow voltage level range bit error rate estimation scan, using the approximate optimal read reference voltage, to determine an optimal read reference voltage for the first string group; and

in a second string group of the plurality of string groups, without performing the broad voltage level range bit error rate estimation scan, performing the narrow voltage level range bit error rate estimation scan, using the approximate optimal read reference voltage for the first string group, to determine an optimal read reference voltage for the second string group,

wherein the broad voltage level range bit error rate estimation scan includes scanning a broader range of voltage levels than the narrow voltage level range bit error rate estimation scan.

9. The method of claim 8 , wherein the approximate optimal read reference voltage for the first string group and the optimal read reference voltage for the first string group are determined by scanning the memory cells of a first word line and the first string group.

10. The method of claim 9 , wherein the optimal read reference voltage for the second string group is determined by scanning the memory cells of the first word line and the second string group.

11. The method of claim 8 , the method further comprising the steps of:

in the first string group, performing the broad voltage level range bit error rate estimation scan to identify an approximate optimal read reference voltage for the memory cells of a second word line and the first string group; and

in the first string group, performing the narrow voltage level range bit error rate estimation scan, using the optimal read reference voltage for the second word line and the first string group, to determine an optimal read reference voltage for the second word line and the first string group.

12. The method of claim 10 , the method further comprising the step of:

in the second string group, performing the narrow voltage level range bit error rate estimation scan for the memory cells of a second word line and the second string group, using the approximate optimal read reference voltage for the second word line and the first string group, to determine an optimal read reference voltage for the second word line and the second string group.

13. The method of claim 8 , the method further comprising the step of:

setting an optimal read reference voltage for a third string group adjacent to the second string group to the optimal read reference voltage for the second string group.

14. The method of claim 10 , the method further comprising the step of:

setting an optimal read reference voltage for a second word line adjacent to the first word line to the optimal read reference voltage for the first word line and the second string.

15. An apparatus, comprising:

a memory block including an array of memory cells that are arranged in a plurality of word lines and in a plurality of NAND strings, the plurality of NAND strings being divided into a plurality of string groups,

a means for performing in a first string group of the plurality of string groups, a broad voltage level range bit error rate estimation scan to identify an approximate optimal read reference voltage for the first string group;

a means for performing in the first string group a narrow voltage level range bit error rate estimation scan, using the approximate optimal read reference voltage, to determine an optimal read reference voltage for the first string group; and

in a second string group of the plurality of string groups, a means for, without performing the broad voltage level range bit error rate estimate scan, performing the narrow voltage level range bit error rate estimation scan, using the approximate optimal read reference voltage for the first string group, to determine an optimal read reference voltage for a second string,

wherein the broad voltage level range bit error rate estimation scan includes scanning a broader range of voltage levels than the narrow voltage level range bit error rate estimation scan.

16. The apparatus of claim 15 , wherein the approximate optimal read reference voltage for the first string group and the optimal read reference voltage for the first string group are determined by scanning the memory cells of a first word line and the first string group.

17. The apparatus of claim 16 , wherein the optimal read reference voltage for the second string group is determined by scanning the memory cells of the first word line and the second string group.

18. The apparatus of claim 15 , further comprising:

in the first string group, a means for performing the broad voltage level range bit error rate estimation scan to identify an approximate optimal read reference voltage for a second word line and the first string group; and

in the first string group, a means for performing the narrow voltage level range bit error rate estimation scan, using the optimal read reference voltage for the second word line and the first string group, to determine an optimal read reference voltage for the second word line and the first string group.

19. The apparatus of claim 18 , further comprising:

a means for performing the narrow voltage level range bit error rate estimation scan for the second word line and the second string group, using the approximate optimal read reference voltage for the second word line and the first string group, to determine an optimal read reference voltage for the second word line and the second string group.

20. The apparatus of claim 15 , further comprising:

a means for setting an optimal read reference voltage for a third string group adjacent to the second string group to the optimal read reference voltage for the second string group.

Assignments (8)

Continuity (1)

References Cited (12)