Encoder supporting multiple code rates and code lengths
View Patent ↗An encoder that supports multiple code rates and code lengths is disclosed. A shift register utilized by the encoder may be scaled in size based on a selected code rate or code length. The shift register shifts a bit series for the matrix without requiring fixed feedback points within the register. The sizes of the matrix and bit series are based on the selected code rate or code length, and the encoder loads the bit series into a first portion of the shift register, and a division of the bit series into a second portion of the shift register located adjacent to the first portion. The encoder periodically repopulates the shift register from memory to simulate circular shifting of the bit series without feedback points. Accordingly, complexity of the encoder is reduced.
1. A method of encoding, comprising:
loading a predetermined bit series of a matrix into a first portion of a shift register, and a first division of a plurality of divisions of the predetermined bit series into a second portion of the shift register adjacent the first portion;
performing a predetermined number of encoding iterations, wherein each encoding iteration comprises executing an operation on a data payload using bit values in the first portion of the shift register and shifting contents of the first and second portions of the shift register one position;
reloading the second portion of the shift register with a next division of the plurality of divisions of the predetermined bit series; and
repeating the performing and reloading steps until the predetermined number of encoding iterations has been performed with each of the plurality of divisions of the predetermined bit series loaded into the second portion of the shift register to generate a codeword from the data payload.
2. The method of claim 1 , further comprising:
identifying a code rate selected from a plurality of predetermined code rates;
determining a matrix size of the matrix based on the identified code rate; and
setting a bit size of the predetermined bit series, a bit size of the first portion, a bit size of the second portion, and a bit size of each division based on the matrix size,
wherein the bit size of the first portion is equal to the bit size of the predetermined bit series, and the bit size of the second portion is equal to the bit size of each division.
3. The method of claim 2 , wherein the matrix is a generator matrix, and the predetermined bit series is a row or column of a circulant of the generator matrix.
4. The method of claim 2 , wherein the predetermined number of encoding iterations is equal to the bit size of the second portion, and wherein the second portion is reloaded with the next division after the predetermined number of encoding iterations are performed.
5. The method of claim 4 , wherein the predetermined bit series is stored in a memory, and wherein the reloading comprises:
reloading the first and second portions of the shift register with respective divisions of the predetermined bit series arranged such that the first portion of the shift register is populated with the predetermined bit series in a circularly-shifted state according to a predetermined number of shifts equal to the bit size of the second portion.
6. The method of claim 2 , wherein the shift register comprises a third portion, wherein a bit size of the third portion is a bit size of the shift register less the bit size of the first portion and the bit size of the second portion.
7. The method of claim 6 , wherein the performing, reloading, and repeating steps operate to simulate a circular shifting of the predetermined bit series within the first portion of the shift register.
8. A data encoding system, comprising:
a controller configured to identify a predetermined code size for host data received from a host system;
a memory storing at least a portion of a matrix for the predetermined code size;
a shift register; and
a controller configured to:
load a predetermined bit series of the matrix into a first portion of the shift register, and a first division of a plurality of divisions of the predetermined bit series into a second portion of the shift register adjacent to the first portion;
perform a predetermined number of encoding iterations, wherein each encoding iteration comprises executing an operation on a data payload using bit values in the first portion of the shift register and shifting contents of the first and second portions of the shift register one position;
reload the second portion of the shift register with a next division of the plurality of divisions of the predetermined bit series; and
repeat the perform and reload steps until the predetermined number of encoding iterations has been performed with each of the plurality of divisions of the predetermined bit series loaded into the second portion of the shift register to generate a codeword from the data payload.
9. The data encoding system of claim 8 , wherein the predetermined code size is identified from a plurality of predetermined code sizes, wherein the controller is further configured to:
determine a matrix size of the matrix based on the identified code size; and
set a bit size of the predetermined bit series, a bit size of the first portion, a bit size of the second portion, and a bit size of each division based on the matrix size,
wherein the bit size of the first portion is equal to the bit size of the predetermined bit series; and the bit size of the second portion is equal to the bit size of each division.
10. The data encoding system of claim 9 , wherein the matrix is a generator matrix, and the bit series is a row or column of a circulant of the generator matrix.
11. The data encoding system of claim 9 , wherein the predetermined number of encoding iterations is equal to the bit size of the second portion, and wherein the second portion is reloaded with the next division after the predetermined number of encoding iterations are performed.
12. The data encoding system of claim 9 , wherein the predetermined bit series is stored in a memory, and wherein the being configured to reload comprises the controller being configured to:
reload the first and second portions of the shift register with respective divisions of the predetermined bit series arranged such that the first portion of the shift register is populated with the predetermined bit series in a circularly-shifted state according to a predetermined number of shifts equal to the bit size of the second portion.
13. The data encoding system of claim 9 , wherein the shift register comprises a third portion, wherein a bit size of the third portion is a bit size of the shift register less the bit size of the first portion and the bit size of the second portion.
14. The data encoding system of claim 13 , wherein the performing, reloading, and repeating steps operate to simulate a circular shifting of the predetermined bit series within the first portion of the shift register.
15. A non-transitory machine-readable medium comprising instructions thereon that, when executed, cause an encoding module to perform a method comprising:
loading a predetermined bit series of a matrix into a first portion of a shift register, and a first division of a plurality of divisions of the predetermined bit series into a second portion of the shift register adjacent the first portion;
performing a predetermined number of encoding iterations, wherein each encoding iteration comprises executing an operation on a data payload using bit values in the first portion of the shift register and shifting contents of the first and second portions of the shift register one position;
reloading the second portion of the shift register with a next division of the plurality of divisions of the predetermined bit series; and
repeating the performing and reloading steps until the predetermined number of encoding iterations has been performed with each of the plurality of divisions of the predetermined bit series loaded into the second portion of the shift register to generate a codeword from the data payload.
16. The non-transitory machine-readable medium of claim 15 , wherein the method further comprises:
identifying a code rate selected from a plurality of predetermined code rates;
determining a matrix size of the matrix based on the identified code rate; and
setting a bit size of the predetermined bit series; a bit size of the first portion, a bit size of the second portion, and a bit size of each division based on the matrix size,
wherein the bit size of the first portion is equal to the bit size of the predetermined bit series, and the bit size of the second portion is equal to the bit size of each division.
17. The non-transitory machine-readable medium of claim 16 , wherein the matrix is a generator matrix, and the bit series is a row or column of a circulant of the generator matrix.
18. The non-transitory machine-readable medium of claim 16 , wherein the predetermined number of encoding iterations is equal to the bit size of the second portion, and wherein the second portion is reloaded with the next division after the predetermined number of encoding iterations are performed.
19. The non-transitory machine-readable medium of claim 16 , wherein the predetermined bit series is stored in a memory, and wherein the reloading comprises:
reload the first and second portions of the shift register with respective divisions of the predetermined bit series arranged such that the first portion of the shift register is populated with the predetermined bit series in a circularly-shifted state according to a predetermined number of shifts equal to the bit size of the second portion.
20. The non-transitory machine-readable medium of claim 19 , wherein the shift register comprises a third portion, wherein a bit size of the third portion is a bit size of the shift register less the bit size of the first portion and the bit size of the second portion.
21. A system, comprising:
a means for loading a predetermined bit series of a matrix into a first portion of a shift register, and a first division of a plurality of divisions of the predetermined bit series into a second portion of the shift register adjacent the first portion;
a means for performing a predetermined number of encoding iterations, wherein each encoding iteration comprises executing an operation on a data payload using bit values in the first portion of the shift register and shifting contents of the first and second portions of the shift register one position;
a means for reloading the second portion of the shift register with a next division of the plurality of divisions of the predetermined bit series; and
a means for repeating the performing and reloading steps until the predetermined number of encoding iterations has been performed with each of the plurality of divisions of the predetermined bit series loaded into the second portion of the shift register to generate a codeword from the data payload.
22. The system of claim 21 , further comprising:
a means for identifying a code rate selected from a plurality of predetermined code rates;
a means for determining a matrix size of the matrix based on the identified code rate; and
a means for setting a bit size of the predetermined bit series, a bit size of the first portion, a bit size of the second portion, and a bit size of each division based on the matrix size,
wherein the bit size of the first portion is equal to the bit size of the predetermined bit series, and the bit size of the second portion is equal to the bit size of each division.