IP Library Granted Patent US 10,162,006
Granted Patent B2
US 10,162,006 · App. 14/689,043 · Granted Dec 25, 2018

Boundary scan testing a storage device via system management bus interface

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Quick Facts
Patent No.
US 10,162,006
App. No.
14/689,043
Granted
Dec 25, 2018
Kind
B2
Abstract

A system and method are provided for boundary scan testing one or more digital data storage drives. In particular, a drive tester system connects to the one or more digital data storage drives via a standard two-wire interface, such as a system management bus (SMBus) interface. The drive tester system performs a boundary scan test on the on more digital data storage drives via the standard two-wire interface. The boundary scan test may include a vector test.

Claims (25)

1. A drive tester system, comprising:

a digital data storage drive including one or more integrated circuits having at least one pair of pins connected via an interconnect;

a system management bus (SMBus) interface having two wire connections with at least one pull-up resistor coupled to each of the wire connections and wherein the pull up resistors are configured to be driven by one of an open drain and open collector transistor output; and

a host tester system coupled to the digital data storage drive via the SMBus interface and configured to carry out a boundary scan test concurrently with a built-in self-test including a burn-in test and an endurance test on the digital data storage drive via the SMBus interface during drive manufacturing, wherein the boundary scan test includes a vector test and the host tester system is configured with an inter-integrated circuit serial bus interface with bidirectional serial lines.

2. The drive tester system of claim 1 , wherein the digital data storage drive is a solid state drive.

3. The drive tester system of claim 1 , wherein the digital data storage drive is a hard disk drive.

4. The drive tester system of claim 1 , wherein the two wire connections include a serial clock line (SCL) and a serial data line (SDA).

5. The drive tester system of claim 1 , wherein the digital data storage drives includes a controller that is configured to port at least one of:

an SMBus protocol; or

an FC protocol.

6. The drive tester system of claim 5 , wherein the controller includes a general purpose microcontroller.

7. The drive tester system of claim 5 , wherein the controller is integrated into a system on chip (SoC) and uses one or more processors on the SoC.

8. The drive tester system of claim 1 , wherein the SMBus interface does not include a universal asynchronous/transceiver (UART) or a high-speed interface (HSSI).

9. The drive tester system of claim 1 , further comprising: at least one other digital data storage drive, wherein the host tester system is further configured to test the digital data storage drives in parallel over the SMBus interface.

10. A method for self-testing a digital data storage drive, the method comprising:

connecting a host tester system to the digital data storage drive via a two-wire system management bus (SMBus) interface with at least one pull-up resistor coupled to each of the two-wires and wherein the pull up resistors are configured to be driven by one of an open drain and open collector transistor output, wherein the digital storage drive includes one or more integrated circuits having at least one pair of pins connected via an interconnect and the host tester system is configured with an inter-integrated circuit serial bus interface with bidirectional serial lines; and

performing a boundary scan test on the digital data storage drive concurrently with a built-in self-test including a burn-in test and an endurance test via the two-wire SMBus interface during drive manufacturing, wherein the boundary scan test includes a vector test.

11. The method of claim 10 , wherein the digital data storage drive is a solid state drive.

12. The method of claim 10 , wherein the digital data storage drive is a hard disk drive.

13. The method of claim 10 , wherein the two wire SMBus interface include a serial clock line (SCL) and a serial data line (SDA).

14. The method of claim 10 , wherein the digital data storage drives includes a controller that is configured to port at least one of:

an SMBus protocol;

or an FC protocol.

15. The method of claim 14 , wherein the controller includes a general purpose microcontroller.

16. The method of claim 14 , wherein the controller is integrated into a system on chip (SoC) and uses one or more processors on the SoC.

Assignments (12)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT SERIAL NO 15/025,946 PREVIOUSLY RECORDED AT REEL: 040831 FRAME: 0265. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 15, 2017
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 043973/0762 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040831/0265 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2015
From: ATHIMOLOM, GOBINATHAN; ROTHBERG, MICHAEL
To: HGST NETHERLANDS B.V.
Reel/Frame 035431/0400 →