Processor in non-volatile storage memory
In one example, a computing system includes a device, the device including: a non-volatile memory divided into a plurality of selectable locations, each bit in the non-volatile memory configured to have corresponding data independently altered, wherein the selectable locations are grouped into a plurality of data lines; and one or more processing units coupled to the non-volatile memory, each of the processing units associated with a data line of the plurality of data lines, and each of the processing units configured to compute, based on data in an associated data line of the plurality of data lines, corresponding results, wherein the non-volatile memory is configured to selectively write, based on the corresponding results, data in selectable locations of the associated data line reserved to store results of the computation from the process unit associated with the associated data line.
1. A computing system, comprising:
a plurality of non-volatile memory units configured to store corresponding data, and instruction sets for performing different operations, each of the instruction sets comprising a plurality of sequentially-executable instructions for performing one of the different operations;
a plurality of first processing units respectively configured to manipulate data within an addressable location of a corresponding non-volatile memory unit of the plurality of non-volatile memory units, the addressable locations being respectively associated with different instructions of the plurality of sequentially-executable instructions, the plurality of first processing units being configured to concurrently execute the different instructions for a respective operation within the corresponding non-volatile memory units; and
at least one second processing unit respectively including the plurality of non-volatile memory units and the plurality of first processing units, the at least one second processing unit being configured to perform the different operations in a sequence on the corresponding data and to reorder, during the sequence, the different operations based on instruction sets most frequently used relative to each other.
2. The computing system of claim 1 , wherein the at least one second processing unit is further configured to power down one or more processing units of the plurality of first processing units not identified for use during the sequence.
3. The computing system of claim 1 , wherein the plurality of non-volatile memory units and the plurality of first processing units comprise components arranged on an integrated circuit.
4. The computing system of claim 1 , wherein the at least one second processing unit is further configured to maintain a queue in memory indicating the most frequently used instruction sets relative to each other.
5. The computing system of claim 4 , wherein the queue comprises an identifier stored for each of the instruction sets.
6. The computing system of claim 4 , wherein the queue comprises a usage value stored for identifying, for each of the instruction sets, a frequency of use of the instruction set.
7. A computing system, comprising:
a non-volatile memory comprising a plurality of data lines having corresponding data, and a plurality of code lines having instruction sets for performing different operations, each of the instruction sets comprising a plurality of sequentially-executable instructions for performing one of the different operations;
a plurality of processing units respectively configured to manipulate data within an addressable location of a memory subarray of the non-volatile memory, the addressable locations corresponding to different data lines of the plurality of data lines, the different data lines being respectively associated with different instructions of the plurality of sequentially-executable instructions, the plurality of processing units being configured to concurrently execute the different instructions for a respective operation within the memory subarrays of the non-volatile memory; and
a processor including the non-volatile memory and the plurality of processing units, the processor configured to order instruction sets most frequently used relative to each other and to perform the different operations in a sequence on the corresponding data for each of the data lines to produce a result,
wherein during the sequence, the processor is configured to reorder the operations based on the order of the instruction sets.
8. The computing system of claim 7 , wherein the processor is further configured to maintain in memory a queue comprising information indicating the most frequently used instruction sets relative to each other.
9. The computing system of claim 8 , wherein the processor is further configured to retrieve, during the sequence, the information from the queue.
10. The computing system of claim 8 , wherein the information comprises a plurality of usage values, each usage value indicating how often a corresponding one of the instruction sets is used to perform an operation on data.
11. The computing system of claim 8 , wherein the information comprises a plurality of identifiers corresponding to the code lines.
12. The computing system of claim 11 , wherein the queue further comprises an optimization window for providing a plurality of identifiers arranged based on the most frequently used instruction sets relative to each other.
13. The computing system of claim 7 , wherein the processor is further configured to store the result of each of the different operations in a dedicated portion of the data line for which the operation was performed.
14. The computing system of claim 7 , wherein the processor is further configured to reorder the operations periodically.
15. A computing system, comprising:
at least one non-volatile memory configured to store corresponding sets of data, and instruction sets for performing different operations;
a plurality of processing units respectively configured to manipulate data within a selectable location of a memory subarray of the at least one non-volatile memory, the selectable locations being respectively associated with different commands within the instruction sets, the plurality of processing units being configured to concurrently execute the different commands for a respective operation within the memory subarrays; and
at least one processor including the at least one non-volatile memory and the plurality of processing units, the at least one processor configured to perform the different operations on the corresponding sets of data in a sequence to produce corresponding results,
wherein during the sequence, the at least one processor is configured to reorder the operations based on a relative frequency of use of the instruction sets.
16. The computing system of claim 15 , wherein the at least one processor is configured to power down one or more processing units of the plurality of processing units not identified for use during the sequence.
17. The computing system of claim 15 , wherein the plurality of processing units and the at least one non-volatile memory comprise components arranged on an integrated circuit.
18. The computing system of claim 15 , wherein the at least one processor is further configured to maintain a queue in memory indicating the relative frequency of use of the instruction sets.
19. The computing system of claim 18 , wherein the queue comprises an identifier corresponding to each of the instruction sets.
20. The computing system of claim 18 , wherein the queue comprises a usage value identifying, for each of the instruction sets, a frequency of use of the instruction set.