IP Library Granted Patent US 8,843,691
Granted Patent B2
US 8,843,691 · App. 12/343,378 · Granted Sep 23, 2014

Prioritized erasure of data blocks in a flash storage device

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Quick Facts
Patent No.
US 8,843,691
App. No.
12/343,378
Granted
Sep 23, 2014
Kind
B2
Abstract

Methods and systems for the prioritized erasure of data blocks in a flash storage device are provided. A data block in the flash storage device is selected for erasure based upon the number of valid data segments therein, thereby minimizing the number of data segments that are carried over to another data block before erasing the selected data block. The overhead of write operations in the flash storage device is therefore greatly reduced, and the overall performance thereof greatly increased. A method for managing memory operations in a flash storage device having a plurality of data blocks comprises the steps of selecting one of the plurality of data blocks for erasure based upon a number of valid data segments therein, and erasing the selected one of the plurality of data blocks.

Claims (41)

1. A method for managing memory operations in a flash storage device having a plurality of data blocks, each block comprising a plurality of data segments, the method comprising the steps of:

providing one or more linked lists comprising a plurality of nodes, each of the plurality of nodes indicating the number of valid data segments in a corresponding one of the plurality of data blocks;

ordering the plurality of nodes in the one or more linked lists based upon the number of valid data segments indicated therein;

selecting one of the plurality of data blocks for erasure based on the ordering of the one or more linked lists such that the selected data block corresponds to one of the plurality of nodes indicating a lowest number of valid data segments; and

erasing the selected data block when an available number of pre-erased data blocks falls below a predetermined amount.

2. The method according to claim 1 , wherein the step of selecting one of the plurality of data blocks for erasure further comprises selecting the data block for erasure based upon a number of invalid data segments therein.

3. The method according to claim 1 , wherein the step of erasing comprises copying the valid data segments of the selected data block to another one of the plurality of data blocks.

4. The method according to claim 3 , wherein the other data block is a pre-erased data block.

5. The method according to claim 1 , wherein the data segments in each of the plurality of data segments comprises 4 kB.

6. The method according to claim 1 , wherein each of the plurality of nodes indicates the number of valid data segments in a corresponding one of the plurality of data blocks by indicating a number of invalid data segments in the corresponding one of the plurality of data blocks.

7. The method according to claim 1 , wherein the lowest number of valid data segments corresponds to a predetermined number of valid data segments.

8. The method according to claim 1 , wherein the one or more linked lists comprise a plurality of linked lists, each of the plurality of linked lists indicating a number of valid data segments in each data block of a distinct subset of the plurality of data blocks, each subset of the plurality of data blocks having a predefined range of valid data segments.

9. The method according to claim 1 , wherein the selected one of the plurality of data blocks corresponds to one of the plurality of nodes at an end of one of the one or more linked lists.

10. The method according to claim 1 , further comprising the step of:

updating the one or more linked lists based upon an operation in the flash storage device which changes the number of valid data segments of one of the plurality of data blocks.

11. The method according to claim 1 , wherein the step of selecting one of the plurality of data blocks for erasure is part of a background maintenance task.

12. The method according to claim 1 , wherein the step of selecting one of the plurality of data blocks for erasure is triggered in response to a rewrite operation of the flash storage device.

13. A flash storage device, comprising:

a plurality of data blocks, each block comprising a plurality of data segments; and

a controller configured to:

provide one or more linked lists comprising a plurality of nodes, each of the plurality of nodes indicating the number of valid data segments in a corresponding one of the plurality of data blocks;

order the plurality of nodes in the one or more linked lists based upon the number of valid data segments indicated therein;

select one of the plurality of data blocks for erasure based on the ordering of the one or more linked lists such that the selected data block corresponds to one of the plurality of nodes indicating a lowest number of valid data segments; and

erase the selected data block when an available number of pre-erased data blocks falls below a predetermined amount.

14. The flash storage device according to claim 13 , wherein the controller is configured to erase the one of the plurality of data blocks by erasing the one of the plurality of data blocks based upon a number of invalid data segments therein.

15. The flash storage device according to claim 13 , wherein the controller is further configured to copy the valid data segments of the selected one of the plurality of data blocks to another one of the plurality of data blocks before erasing the selected one of the plurality of data blocks.

16. The flash storage device according to claim 15 , wherein the another one of the plurality of data blocks is a pre-erased data block.

17. The flash storage device according to claim 13 , wherein the data segments in each of the plurality of data segments comprises 4 kB.

18. The flash storage device according to claim 13 , further comprising a machine-readable medium configured to store the one or more linked lists.

19. The flash storage device according to claim 13 , wherein each of the plurality of nodes indicates the number of valid data segments in a corresponding one of the plurality of data blocks by indicating a number of invalid data segments in the corresponding one of the plurality of data blocks.

20. The flash storage device according to claim 13 , wherein the lowest number of valid data segments corresponds to a predetermined number of valid data segments.

21. The flash storage device according to claim 13 , wherein the one or more linked lists comprise a plurality of linked lists, each of the plurality of linked lists indicating a number of valid data segments in each data block of a distinct subset of the plurality of data blocks, each subset of the plurality of data blocks having a predefined range of valid data segments.

22. The flash storage device according to claim 13 , wherein the selected one of the plurality of data blocks corresponds to one of the plurality of nodes at an end of one of the one or more linked lists.

23. The flash storage device according to claim 13 , wherein the controller is further configured to update the one or more linked lists based upon an operation in the flash storage device which changes the number of valid data segments of one of the plurality of data blocks.

24. The flash storage device according to claim 13 , wherein the controller is configured to select one of the plurality of data blocks for erasure as part of a background maintenance task.

25. The flash storage device according to claim 13 , wherein the controller is configured to select one of the plurality of data blocks for erasure in response to a rewrite operation of the flash storage device.

26. A non-transitory machine readable medium storing one or more sequences of instructions for managing memory operations in a flash storage device having a plurality of data blocks, each block comprising a plurality of data segments, wherein execution of the one or more sequences of instructions by one or more processors causes the one or more processors to perform the steps of:

providing one or more linked lists comprising a plurality of nodes, each of the plurality of nodes indicating the number of valid data segments in a corresponding one of the plurality of data blocks;

ordering the plurality of nodes in the one or more linked lists based upon the number of valid data segments indicated therein;

selecting one of the plurality of data blocks for erasure based on the ordering of the one or more linked lists such that the selected data block corresponds to one of the plurality of nodes indicating a lowest number of valid data segments; and

erasing the selected one of the plurality of data blocks when an available number of pre-erased data blocks falls below a predetermined amount.

Assignments (12)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2018
From: HGST TECHNOLOGIES SANTA ANA, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046174/0446 →
CHANGE OF NAME Recorded Jul 1, 2015
From: STEC, INC.
To: HGST TECHNOLOGIES SANTA ANA, INC.
Reel/Frame 036042/0390 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2009
From: CALVERT, WILLIAM; BOORMAN, STEPHEN RUSSELL; HAYNES, SIMON MARK
To: STEC, INC.
Reel/Frame 022504/0801 →