IP Library Granted Patent US 11,630,785
Granted Patent B2
US 11,630,785 · App. 17/184,529 · Granted Apr 18, 2023

Data storage with improved data transfer

Inventors: Refael Ben-Rubi (Rosh Haayin, IL); Moshe Cohen (Modi'in, IL)
Assignee: Western Digital Technologies, Inc.
G06F13/1668
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Quick Facts
Patent No.
US 11,630,785
App. No.
17/184,529
Granted
Apr 18, 2023
Kind
B2
Abstract

The present disclosure generally relates to improving data transfer speed. A data storage device includes both a controller and a memory device. The controller provides instructions regarding read and/or write commands to the memory device through the use of control lines. The data to be written/read is transferred between the controller and the memory device along data lines. The control lines typically are not used during data transfer. During data transfer, the control lines can be used to increase data transfer speed by utilizing the otherwise idle control lines for data transfer in addition to the data lines. Hence, data transfer speed is increased by using not only the data lines, but additionally the control lines. Once the data transfer is complete, the control lines return to their legacy function.

Claims (41)

1. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to:

send or receive data along one or more data lines coupling the memory device to the controller, wherein the one or more data lines operate at a first rate;

send or receive data along one or more control lines coupling the memory device to the controller, wherein the one or more control lines operate at a second rate that is less than the first rate;

take data from an original order and transmit data along the one or more data lines and the one or more control lines in parallel; and

accept and reorder the data transmitted along the one or more data lines and the one or more control lines into the original order.

2. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to:

send or receive data along one or more data lines coupling the memory device to the controller, wherein the one or more data lines operate at a first rate;

send or receive data along one or more control lines coupling the memory device to the controller, wherein the one or more control lines operate at a second rate that is less than the first rate; and

instruct the memory device to send data along the one or more control lines; and

instruct the memory device to switch the one or more control lines from functioning as a data line back to functioning as a control line.

3. A data storage device, comprising:

one or more memory devices, the one or more memory devices comprising a plurality of first input/output devices, wherein the plurality of first input/output devices are capable of driving a signal bi-directionally;

a controller coupled to the one or more memory devices, the controller comprising a flash interface module, wherein the flash interface module comprises a plurality of second input/output devices, wherein the plurality of second input/output devices are capable of driving a signal bi-directionally;

one or more first data lines coupled between the plurality of first input/output devices and the plurality of second input/output devices; and

one or more first control lines coupled between the plurality of first input/output devices and the plurality of second input/output devices, wherein the controller is configured to:

instruct the one or more memory devices and the flash interface module to switch the one or more first control lines from functioning as a control line to function as a data line;

instruct the one or more memory devices and the flash interface module to send data along the one or more first control lines; and

instruct the one or more memory devices and the flash interface module to switch the one or more first control lines from functioning as the data line back to functioning as the control line.

4. A data storage device, comprising:

a memory device;

a controller coupled to the memory device, wherein the controller is configured to:

instruct the memory device to transfer a predetermined number of bytes;

instruct the memory device to use the control lines for transferring the predetermined number of bytes; and

instruct the memory device to automatically change functionality of the control lines to function as control lines rather than data lines upon completion of the transferring; and

means to transfer data between the memory device and the controller along both data lines and control lines, wherein the data lines are distinct from the control lines, and wherein the data lines are configured to transfer data at a greater speed than the control lines.

5. The data storage device of claim 1 , wherein the one or more data lines comprises at least eight data lines.

6. The data storage device of claim 1 , wherein the one or more control lines comprises a write protect line, a command latch enable line, an address latch enable line, and a chip enable line.

7. The data storage device of claim 2 , wherein the controller instructs the memory device using the one or more control lines.

8. The data storage device of claim 2 , wherein the controller instructs the memory device prior to the memory device sending data along the one or more control lines.

9. The data storage device of claim 3 , wherein the plurality of first input/output devices comprise transistors.

10. The data storage device of claim 9 , wherein the plurality of second input/output devices comprise transistors.

11. The data storage device of claim 3 , wherein the one or more memory devices comprises a first memory device and a second memory device.

12. The data storage device of claim 11 , wherein the controller is configured to instruct the first memory device to transmit data along the one or more first control lines.

13. The data storage device of claim 11 , wherein the controller is configured to transmit data between the controller and the first memory device nonparallel in time with transmitting data between the controller and the second memory device.

14. The data storage device of claim 11 , wherein the controller is configured to ensure that, after transmitting data to or from the first memory device, the plurality of second input/output devices have returned to a legacy mode prior to sending or receiving data or control information to the second memory device, wherein the legacy mode is capable of transmitting control signals from the controller.

15. The data storage device of claim 4 , wherein the means to transfer data between the memory device and the controller along both data lines and control lines is capable of driving a signal bi-directionally.

16. The data storage device of claim 4 , wherein the control lines operate at a frequency lower than a frequency at which the data lines operate.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2021
From: BEN-RUBI, REFAEL; COHEN, MOSHE
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055431/0435 →