IP Library Granted Patent US 10,224,928
Granted Patent B1
US 10,224,928 · App. 15/934,379 · Granted Mar 5, 2019

On-die impedance calibration

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Quick Facts
Patent No.
US 10,224,928
App. No.
15/934,379
Granted
Mar 5, 2019
Kind
B1
Abstract

Apparatuses, systems, methods, and computer program products are disclosed for on-die impedance calibration. A calibration circuit determines a digital compensation value for an input/output driver. A calibration adjustment circuit provides a digital compensation value to a calibration circuit to produce an analog output corresponding to the digital compensation value. A feedback circuit provides an analog output as feedback to a calibration circuit to produce an analog compensation value.

Claims (30)

1. An apparatus comprising:

a calibration circuit that determines a digital compensation value for an input/output driver;

a calibration adjustment circuit that provides the digital compensation value to the calibration circuit to produce an analog output corresponding to the digital compensation value; and

a feedback circuit that provides the analog output as feedback to the calibration circuit to produce an analog compensation value.

2. The apparatus of claim 1 , wherein the digital compensation value is determined from an analog value.

3. The apparatus of claim 2 , wherein the digital compensation value is rounded down to a nearest digital value that has an analog equivalent that is less than the analog value.

4. The apparatus of claim 3 , wherein the analog value is a sum of the analog equivalent and the analog compensation value.

5. The apparatus of claim 1 , wherein the calibration circuit produces a calibration completion output in response to determining the digital compensation value.

6. The apparatus of claim 5 , wherein the feedback circuit produces the analog compensation value in response to the calibration completion output being produced.

7. The apparatus of claim 5 , further comprising a control circuit that receives an indication of the calibration completion output and provides an enable output to the feedback circuit to enable the feedback circuit.

8. The apparatus of claim 7 , wherein the control circuit provides a calibration adjustment completion output in response to producing the analog compensation value.

9. The apparatus of claim 1 , wherein the feedback circuit comprises an amplifier that outputs the analog compensation value based on inputs comprising the analog output and a reference voltage based on a supply voltage.

10. The apparatus of claim 1 , wherein the calibration circuit determines a plurality of digital compensation values comprising the digital compensation value, and the feedback circuit determines a plurality of analog compensation values comprising the analog compensation value.

11. A method comprising:

receiving a digital impedance input;

receiving an analog impedance input;

providing the digital impedance input and the analog impedance input to an impedance matching circuit to produce an analog result; and

determining a local digital impedance output based on the digital impedance input, the analog impedance input, and the analog result.

12. The method of claim 11 , wherein determining the local digital impedance output comprises applying a trim digital impedance input to the impedance matching circuit.

13. The method of claim 12 , wherein an initial value for the trim digital impedance input is determined based on the digital impedance input.

14. The method of claim 13 , wherein the initial value for the trim digital impedance input is determined by looking up the digital impedance input in a table.

15. The method of claim 12 , further comprising adjusting the trim digital impedance input until the analog result matches a predetermined voltage.

16. The method of claim 15 , further comprising storing the trim digital impedance input as the local digital impedance output in response to the analog result matching the predetermined voltage.

17. The method of claim 11 , further comprising producing a local analog impedance output based on the local digital impedance output and the analog impedance input.

18. An apparatus comprising:

means for generating an analog impedance compensation value, for an electrical signal driver, based on a digital impedance compensation value;

means for generating a local analog impedance compensation value at the electrical signal driver; and

means for generating an output voltage based on the digital impedance compensation value, the analog impedance compensation value, and the local analog impedance compensation value.

19. The apparatus of claim 18 , further comprising means for accessing a local digital impedance compensation value at the electrical signal driver.

20. The apparatus of claim 18 , wherein the means for generating the local analog impedance compensation value comprises means for receiving the analog impedance compensation value and the local digital impedance compensation value, and means for producing the local analog impedance compensation value based on the analog impedance compensation value and the local digital impedance compensation value.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2018
From: MATHUR, SHIV HARIT; SUBRAMANIAN, RAMAKRISHNAN; GUPTA, NITIN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046998/0444 →
Cited By (1)
US 12,451,170