Granted Patent B2

US 11,430,531 · App. 17/171,637 · Granted Aug 30, 2022

Inventors: Alexander Bazarsky (Holon, IL); David Rozman (Kiryat Malakhi, IL); Eran Sharon (Rishon Lezion, IL)

Assignee: Western Digital Technologies, Inc.

G11C16/3459G11C11/5642G11C16/0483G11C16/10G11C16/26G11C16/3418G11C16/3436G11C2207/2254G11C2207/2281

Abstract

Claims (58)

1. An apparatus, comprising:

a communication interface; and

a control circuit coupled to the communication interface, wherein the control circuit is configured to connect to non-volatile memory cells, wherein the control circuit is configured to:

apply one or more reference voltages to a set of the non-volatile memory cells;

sense the set of the non-volatile memory cells for a plurality of different integration times while applying the one or more reference voltages to the set of the non-volatile memory cells to generate sensing results;

determine a bit of information for each memory cell in the set for each of the different integration times for the sensing results; and

calibrate an integration time for at least one reference voltage of the one or more reference voltages based on the bit of information for each memory cell in the set for each of the different integration time.

2. The apparatus of claim 1 , wherein the control circuit is configured to calibrate the integration time for the at least one reference voltage based on a bit error rate estimation scan (BES) using the sensing results.

3. The apparatus of claim 1 , wherein the control circuit is configured to:

generate codewords for data stored in the set of the non-volatile memory cells based on the sensing results; and

calibrate the integration time for the at least one reference voltage based on an error metric of each of the codewords.

4. The apparatus of claim 3 , wherein the control circuit is configured to:

emulate sensing for a plurality of integration-time/reference-voltage combinations based on the sensing results for a plurality of the one or more reference voltages; and

generate the codewords based on the emulating sensing for the plurality of integration-time/reference-voltage combinations.

5. The apparatus of claim 1 , wherein:

the one or more reference voltages comprise a plurality of reference voltages for sensing a page of data; and

the control circuit is configured to calibrate a separate integration time for each of the plurality of reference voltages based on the sensing results.

6. The apparatus of claim 1 , wherein to sense the set of the non-volatile memory cells for the plurality of different integration times while applying the one or more reference voltages to the set of the non-volatile memory cells, the control circuit is configured to, for each memory cell in the set and for each integration time:

establish an initial voltage on each of a plurality of sense nodes, each sense node is associated with one of the memory cells;

connect each sense node to the associated memory cell after establishing the initial voltages on the sense nodes; and

detect a voltage on each sense node after waiting for the integration time after connecting the sense nodes to the associated memory cells.

7. The apparatus of claim 1 , wherein the control circuit is configured to:

calibrate the integration time for the at least one reference voltage in response to failing to decode a codeword read from the set of the memory cells; and

recover the codeword based on sensing the memory cells using the integration time for the at least one reference voltage.

8. The apparatus of claim 1 , wherein the control circuit is further configured to:

apply the one or more reference voltages to the set of the non-volatile memory cells after calibrating the integration time for the at least one reference voltage;

sense the set of the memory cells using the calibrated integration time for the at least one reference voltage to generate data results; and

decode a codeword stored in the set of the memory cells based on the data results.

9. A method comprising:

applying a set of reference voltages to a word line connected to a group of non-volatile memory cells;

sensing the group of the non-volatile memory cells for a plurality of different of integration times while applying each reference voltage in the set of reference voltages to the word line to generate sensing results;

generating codewords for data stored in the group of the non-volatile memory cells based on the sensing results, including determining a page of information for each of the different integration times based on the sensing results, wherein the page of information comprises a bit for each memory cell in the group; and

calibrating an integration time for each reference voltage in the set of reference voltages based on error metrics for the codewords, including calibrating a separate integration time for each reference voltage in the set of reference voltages based the page of information for each of the different integration times.

10. The method of claim 9 , wherein generating the codewords for the data stored in the group of the non-volatile memory cells based on the sensing results comprises:

emulating sensing for a plurality of integration-time/reference-voltage combinations based on the sensing results; and

generating the codewords based on the emulating sensing for the plurality of integration-time/reference-voltage combinations.

11. The method of claim 9 , wherein sensing a particular memory cell of the non-volatile memory cells for the plurality of different of integration times while applying a given one of the reference voltages to the word line comprises performing the following for each integration time:

charging a sense capacitor associated with the particular memory cell to an initial voltage;

connecting the sense capacitor to the particular memory cell after charging the sense capacitor to the initial voltage to discharge the initial voltage from the sense capacitor; and

testing a voltage on the sense capacitor after discharging the sense capacitor for the integration time.

12. A non-volatile storage system, comprising:

non-volatile memory cells;

a word line connected to the memory cells;

a plurality of bit lines, each of the bit lines associated with one of the memory cells;

a power control module configured to provide a reference voltage to the word line;

means for programming a set of the non-volatile memory cells to threshold voltage distributions;

means for sensing the set of the memory cells for a plurality of integration times while the reference voltage is applied to the word line to generate a sensing result for each integration time of the plurality of integration times;

means for searching for a valley between two of the threshold voltage distributions based on the sensing result for each integration time; and

means for calibrating an integration time for the reference voltage based on a location of the valley.

13. The non-volatile storage system of claim 12 , wherein the means for sensing the set of the memory cells for the plurality of integration times while the reference voltage is applied to the word line is configured to, for each respective integration time:

determine, for each memory cell in the set, whether the memory cell conducts a current in response to the respective integration time; and

determine a number of bit flips between results for the respective integration time and results for another integration time.

14. The non-volatile storage system of claim 13 , wherein the means for calibrating the integration time for the reference voltage based on the location of the valley is configured to:

calibrate the integration times based on the bit flips.

15. The non-volatile storage system of claim 12 , wherein the means for sensing the set of the memory cells for the plurality of integration times while the reference voltage is applied to the word line is configured to, for each respective integration time:

charge a plurality of sense nodes to an initial voltage, wherein each sense node is associated with one of the memory cells in the set;

connect each memory cell in the set to its associated sense node to allow the memory cell to discharge the sense node for the respective integration time; and

compare a voltage on each sense node with a trip voltage in response to the memory cell discharging the associated sense node for the respective integration time.

Assignments (10)

Continuity (2)

Cited By (2)

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