Granted Patent B2

US 12,417,030 · App. 17/933,823 · Granted Sep 16, 2025

Inventors: Julian Vlaiko (Kfar Saba, IL); Siddhesh Darne (Milpitas, CA); Hanan Borukhov (Rehovot, IL); Venky Ramachandra (San Jose, CA); Grishma Shah (San Jose, CA); Dmitry Vaysman (San Jose, CA)

Assignee: Sandisk Technologies, Inc.

G06F3/0619G06F3/0653G06F3/0679

Abstract

Claims (62)

1. A storage device, comprising:

a memory; and

a controller coupled to the memory and configured to:

generate first data integrity information based on at least one write data byte to be written to the memory, wherein the first data integrity information comprises cyclic redundance check (CRC) information generated based on the at least one write data byte, wherein the CRC information comprises a plurality of CRC bits;

transfer a plurality of write data bytes on a first output to the memory;

toggle each CRC bit of the plurality of CRC bits on a second output based on a respective write data byte of the plurality of write data bytes when transferring the plurality of write data bytes to the memory; and

transfer the at least one write data byte contemporaneously with the first data integrity information on separate data paths to the memory.

2. The storage device of claim 1 , wherein the second output comprises a data bus inversion (DBI) output.

3. The storage device of claim 1 , wherein the controller is further configured to:

receive an indication of whether an error exists in the at least one write data byte based on the first data integrity information.

4. The storage device of claim 1 , wherein the controller comprises:

a data integrity check circuit configured to:

receive at least one read data byte that is read from the memory;

receive second data integrity information from the memory; and

detect whether an error exists in the at least one read data byte based on the second data integrity information.

5. The storage device of claim 2 , wherein the controller is further configured to:

switch between a data bus inversion (DBI) path and a data integrity path to the memory based on whether a data integrity protection mode is active between the memory and the controller.

6. The storage device of claim 5 , wherein the controller is further configured to:

select the data integrity path when the data integrity protection mode is active between the memory and the controller, wherein the first data integrity information is transferred on the data integrity path to the memory.

7. The storage device of claim 5 , wherein the controller is further configured to:

select the DBI path when the data integrity protection mode is not active between the memory and the controller; and

transfer a DBI signal on the DBI path via the second output to the memory.

8. The storage device of claim 4 , wherein the data integrity check circuit is further configured to:

generate expected information based on a data integrity algorithm and the at least one read data byte; and

compare the expected information with the second data integrity information,

wherein the detection of whether the error exists is further based on the comparison of the expected information with the second data integrity information.

9. A storage device, comprising:

a controller; and

a memory coupled to the controller and configured to:

receive a plurality of write data bytes on a first input from the controller, wherein the plurality of write data bytes include a first write data byte to be written to the memory;

receive first data integrity information from the controller, wherein the first write data byte and the first data integrity information are received on separate data paths between the controller and the memory, wherein the first data integrity information comprises cyclic redundance check (CRC) information generated based on the first write data byte, and wherein the CRC information comprises a plurality of CRC bits;

receive each CRC bit of the plurality of CRC bits toggled on a second input based on a respective write data byte of the plurality of write data bytes when the plurality of write data bytes are received from the controller;

detect whether an error exists in the first write data byte based on the first data integrity information; and

write the first write data byte into the memory in response to detecting that the error does not exist in the first write data byte.

10. The storage device of claim 9 , wherein the second input comprises a data bus inversion (DBI) input, wherein the memory is further configured to:

switch between a data bus inversion (DBI) path and a data integrity path within the memory based on whether a data integrity protection mode is active between the memory and the controller.

11. The storage device of claim 9 , wherein the memory is further configured to:

provide an indication of whether an error exists in the first write data byte based on the first data integrity information.

12. The storage device of claim 9 , wherein the memory comprises:

a data integrity generator circuit configured to:

generate second data integrity information based on at least one read data byte that is read from the memory; and

transfer the at least one read data byte contemporaneously with the second data integrity information on separate data paths to the controller.

13. The storage device of claim 9 , wherein the memory comprises:

a data integrity check circuit configured to:

generate expected information based on a data integrity algorithm and the first write data byte; and

compare the expected information with the first data integrity information,

wherein the detection of whether the error exists is further based on the comparison of the expected information with the first data integrity information.

14. The storage device of claim 10 , wherein the memory is further configured to:

select the data integrity path when the data integrity protection mode is active between the memory and the controller, wherein the first data integrity information is transferred on the data integrity path from the controller.

15. The storage device of claim 10 , wherein the memory is further configured to:

select the DBI path when the data integrity protection mode is not active between the memory and the controller; and

receive a DBI signal on the DBI path via the second input at the memory.

16. An apparatus, comprising:

a memory;

a data integrity generator circuit connected to the memory and configured to:

generate first data integrity information based on at least one write data byte to be written to the memory, wherein the first data integrity information comprises cyclic redundance check (CRC) information generated based on the at least one write data byte, wherein the CRC information comprises a plurality of CRC bits;

transfer a plurality of write data bytes on a first output to the memory; and

toggle each CRC bit of the plurality of CRC bits on a second output based on a respective write data byte of the plurality of write data bytes when transferring the plurality of write data bytes to the memory; and

a data integrity check circuit connected to the memory and configured to:

receive at least one read data byte that is read from the memory,

receive second data integrity information from the memory, and

detect whether an error exists in the at least one read data byte based on the second data integrity information.

Assignments (9)

Continuity (1)

References Cited (8)