IP Library Granted Patent US 11,755,459
Granted Patent B2
US 11,755,459 · App. 17/210,091 · Granted Sep 12, 2023

Management of a debug buffer based on priority information

Inventors: Amir Segev (Meiter, IL); Shay Benisty (Beer Sheva, IL)
Assignee: Western Digital Technologies, Inc.
G06F11/3656G06F3/0619G06F3/0656G06F3/0679G06F11/0781G06F11/1068G06F11/366G06F12/1081
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Quick Facts
Patent No.
US 11,755,459
App. No.
17/210,091
Granted
Sep 12, 2023
Kind
B2
Abstract

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive new debug information, determine that a debug buffer does not have any available free entries for the new debug information, compare the priority information to a lowest priority information of old debug information stored in the debug buffer, remove a most recent old debug information that has a lowest priority information from the debug buffer, and place the new debug information and corresponding priority information in the debug buffer.

Claims (31)

1. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to:

receive new debug information, wherein the new debug information includes priority information;

determine that a debug buffer does not have any available free entries for the new debug information;

compare the priority information to a lowest priority information of old debug information stored in the debug buffer;

remove either a most recently stored old debug information that has a lowest priority information or a least recently stored old debug information that has a lowest priority information from the debug buffer;

place the new debug information and corresponding priority information in the debug buffer; and

distribute available bandwidth for transmitting data through a direct memory access (DMA) among a plurality of tenants, wherein an extra virtual tenant is for debug information, wherein the extra virtual tenant is not included in the plurality of tenants, and wherein remaining available bandwidth is distributed to at least one of the extra virtual tenant and one or more tenants of the plurality of tenants.

2. The data storage device of claim 1 , wherein the controller is further configured to:

monitor bandwidth;

request debug information from the debug buffer;

send debug information from the debug buffer to a direct memory access (DMA) module; and

remove debug data from the debug buffer, wherein the removed debug data sent to the DMA.

3. The data storage device of claim 2 , wherein the debug data is removed from the debug buffer prior to being sent to the DMA.

4. The data storage device of claim 1 , wherein the controller is further configured to determine that the debug buffer has space and store debug information in the debug buffer.

5. The data storage device of claim 1 , wherein the controller is further configured to determine whether new debug information has priority information that is less than or equal to the priority information of the lowest priority information data in the debug buffer.

6. The data storage device of claim 1 , wherein the DMA comprises a bandwidth monitor that distributes the available bandwidth.

7. The data storage device of claim 1 , wherein the controller further comprises an information collection module that delivers debug information to a DMA.

8. The data storage device of claim 7 , wherein the information collection module collects debug information and categorizes the debug information according to importance.

9. A data storage device, comprising:

means for storing data; and

a controller coupled to the means for storing data, wherein the controller is configured to:

collect debug information;

collect priority information of the collected debug information;

store the debug information and the priority information in a debug buffer;

remove old debug information from the debug buffer without sending the old debug information to a direct memory access (DMA);

send remaining debug information from the debug buffer to the DMA after removing old debug information from the debug buffer, wherein the remaining debug information is distinct from the old debug information; and

distribute available bandwidth for transmitting data through the DMA among a plurality of tenants, wherein an extra virtual tenant is for the debug information, wherein the extra virtual tenant is not included in the plurality of tenants, and wherein remaining available bandwidth is distributed to at least one of the extra virtual tenant and one or more tenants of the plurality of tenants.

10. The data storage device of claim 9 , wherein the remaining debug information has a higher priority rating than the old debug information.

11. The data storage device of claim 9 , further comprising a bandwidth monitor for requesting debug information from the debug buffer.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2021
From: SEGEV, AMIR; BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055697/0440 →
Continuity (1)
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