Granted Patent B2

US 10,409,747 · App. 15/971,971 · Granted Sep 10, 2019

Abstract

Claims (33)

1. A system, comprising:

interface means for processing requests between a host and a flash storage, the interface means comprising a first means associated with a first communication protocol and a second means associated with a second communication protocol different than the first communication protocol;

transfer means for performing a direct memory access operation to transfer data between the host and the flash storage through the first means using the first communication protocol when a select signal from the host indicates the first communication protocol, and for transferring the data between the host and the flash storage through the second means when the select signal indicates the second communication protocol;

means for processing a request signal from the host, the request signal indicating a request for the direct memory access operation;

means for providing, in response to the request signal, a notification signal indicating receipt of the request from the host;

means for receiving a response signal indicating readiness to transfer data for the request;

means for sending a ready signal to the host based on the received response signal; and

means for receiving an acknowledgement signal from the host based on the sent ready signal,

wherein the system causes the direct memory access operation to be performed subsequent to the receiving the acknowledgment signal.

2. The system of claim 1 , wherein the interface means comprises the means for processing a request signal from the host, the means for providing, in response to the request signal, the notification signal, the means for receiving the response signal, the means for sending the ready signal, and the means for receiving the acknowledgement signal.

3. The system of claim 1 , wherein the transfer means is configured to transfer the data from a starting predetermined address in the flash storage independent of the host providing an address of the flash storage for the direct memory access operation.

4. The system of claim 1 , further comprising:

means for storing a plurality of predetermined addresses of the flash storage;

means for obtaining at least one predetermined address from the plurality of predetermined addresses stored in the means for storing;

means for determining whether the direct memory access operation is a read or write operation;

means for transferring the data from the flash storage at sequential addresses starting at the at least one predetermined address when the direct memory access operation is a read operation; and

means for transferring the data to the flash storage at sequential addresses starting at the at least one predetermined address when the direct memory access operation is a write operation.

5. The system of claim 4 , wherein the transfer means comprises the means for obtaining the at least one predetermined address, the means for determining whether the direct memory access operation is the read or write operation, the means for transferring the data from the flash storage at sequential addresses starting at the at least one predetermined address when the direct memory access operation is a read operation, and the means for transferring the data to the flash storage at sequential addresses starting at the at least one predetermined address when the direct memory access operation is a write operation.

6. The system of claim 1 , wherein the request signal is processed by the first means when the select signal indicates the first communication protocol.

7. The system of claim 1 , wherein the request signal is processed by the second means when the select signal indicates the second communication protocol.

8. The system of claim 1 , wherein the transfer means is configured to write the data into the flash storage in the direct memory access operation when the select signal indicates the first communication protocol.

9. The system of claim 8 , wherein the interface means comprises:

means for receiving a write signal over a control bus to the host;

means for receiving, subsequent to receiving the write signal, a first data block of a sequence of data blocks from the host, the write signal being asserted at start of the first data block; and

means for providing the first data block to the transfer means, the write signal being deasserted by the host according to the first communication protocol.

10. The system of claim 9 , wherein the first communication protocol specifies a minimum time between assertion and deassertion of the write signal.

11. The system of claim 1 , wherein the transfer means is configured to read the data from the flash storage in the direct memory access operation when the select signal indicates the second communication protocol.

12. The system of claim 11 , wherein the interface means comprises:

means for receiving a first data block of a sequence of data blocks from the transfer means;

means for asserting a read signal over a control bus to the host;

means for sending the first data block to the host, the read signal being asserted at start of the first data block; and

means for deasserting the read signal according to the second communication protocol.

13. The system of claim 12 , wherein the second communication protocol specifies a minimum time between assertion and deassertion of the read signal.

Assignments (13)