Method of making ovonic threshold switch selectors using microwave annealing
A method includes forming a first electrode layer over a substrate, forming an ovonic threshold switch (OTS) material layer over the first electrode layer, microwave annealing the OTS material layer, and forming a second electrode layer over the OTS material layer.
1. A method, comprising:
forming a first electrode layer over a substrate;
forming an ovonic threshold switch (OTS) material layer over the first electrode layer;
microwave annealing the OTS material layer; and
forming a second electrode layer over the OTS material layer.
2. The method of claim 1 , wherein the microwave annealing the OTS material layer occurs without exposing any metallic material to microwave radiation during the microwave annealing.
3. The method of claim 2 , further comprising forming bit lines over the substrate prior to forming the first electrode layer, wherein the first electrode layer is formed over the bit lines.
4. The method of claim 3 , further comprising:
patterning the bit lines such that ends of the bit lines are recessed from edges of the substrate; and
covering the recessed ends of the bit lines with at least one overlying non-metallic layer prior to the microwave annealing, such that the metallic material of the bit lines is not exposed to the microwave radiation.
5. The method of claim 4 , wherein the at least one overlying non-metallic layer comprises the OTS material layer.
6. The method of claim 4 , wherein the at least one overlying non-metallic layer comprises a non-metallic carbon-based electrode layer of the first electrode layer.
7. The method of claim 4 , further comprising patterning the first electrode layer such that edges of the first electrode layer are recessed from the edges of the substrate.
8. The method of claim 7 , further comprising covering the recessed edges of the first electrode layer with the at least one overlying non-metallic layer prior to the microwave annealing, such that the metallic material of the first electrode layer is not exposed to the microwave radiation.
9. The method of claim 8 , wherein the at least one overlying non-metallic layer comprises the OTS material layer.
10. The method of claim 3 , further comprising oxidizing ends of the bit lines to form non-metallic metal oxide sidewall spacers on the ends of the bit lines prior to the microwave annealing, such that the metallic material of the bit lines is not exposed to the microwave radiation.
11. The method of claim 1 , further comprising oxidizing edges of the first electrode layer to form non-metallic metal oxide sidewall spacers on the edges of the first electrode layer prior to the microwave annealing, such that a metallic material of the first electrode layer is not exposed to the microwave radiation.
12. The method of claim 1 , wherein the first electrode layer consists essentially of a non-metallic first carbon-based electrode layer.
13. The method of claim 1 , wherein the microwave annealing reduces a first fire voltage of the OTS material layer.
14. The method of claim 1 , wherein the microwave annealing reduces a threshold voltage drift of the OTS material layer.
15. The method of claim 1 , wherein the microwave annealing reduces an optical band gap and increases an amount of arsenic-tellurium bonding in the OTS material layer.
16. The method of claim 1 , wherein the microwave annealing generates conducting clusters in the OTS material layer.
17. The method of claim 1 , wherein the microwave annealing comprises pulsed microwave annealing.
18. The method of claim 1 , wherein the microwave annealing comprises continuous microwave annealing.
19. The method of claim 1 , wherein the OTS material layer comprises a GeSeAsTe material.
20. The method of claim 1 , further comprising:
forming a magnetoresistive random access memory (MRAM) memory element layer above the second electrode layer or below the first electrode layer; and
patterning the MRAM memory element layer, the first electrode layer, the OTS material layer and the second electrode layer into memory pillar structures.