IP Library Granted Patent US 11,164,073
Granted Patent B2
US 11,164,073 · App. 15/981,719 · Granted Nov 2, 2021

Systolic neural network processor with feedback control

Inventors: Luiz M. Franca-Neto (Sunnyvale, CA); Luis V. Cargnini (San Jose, CA)
Assignee: Western Digital Technologies, Inc.
G06N3/063G06F15/8046G06N3/04G06N3/0481G06N3/08G06N3/084G06N5/046
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Quick Facts
Patent No.
US 11,164,073
App. No.
15/981,719
Granted
Nov 2, 2021
Kind
B2
Abstract

At least a subset of first processing units of a first arrangement of an array of processing units is assigned to perform computations of a first layer of a neural network and at least a subset of second processing units of a last arrangement is assigned to perform computations of a second layer. At least a second subset of the first processing units of the first arrangement is re-assigned to perform computations of a third layer. In one aspect, it is determined that a number of layers exceeds a number of arrangements of processing units of a systolic processing chip. A first arrangement of processing units of the number of arrangements is assigned to perform computations according to a first layer for a first set of forward propagations, and the first arrangement is assigned to perform computations according to a different layer for a second set of forward propagations.

Claims (77)

1. A device for performing computations of a neural network comprising at least first, second, and third layers, the device comprising:

an array of processing units including at least:

a first arrangement of first processing units, and

a last arrangement of second processing units,

wherein data is systolically pulsed from arrangement to arrangement of the array;

a controller configured to assign the first and second processing units to perform computations of particular nodes of the at least first, second, and third layers of the neural network; and

a memory configured to store activation output values received from the last arrangement;

wherein:

the controller is configured to:

assign at least a first subset of the first processing units of the first arrangement to perform computations of particular nodes of the first layer of the neural network; and

assign at least a subset of the second processing units of the last arrangement to perform computations of particular nodes of the second layer of the neural network;

the at least a first subset of the first processing units is configured to process inputs into the neural network to generate first activation output values that are systolically pulsed through the array;

the at least a subset of the second processing units of the last arrangement is configured to process received data to generate second activation output values and send the second activation output values to the memory;

the controller is further configured to re-assign at least a second subset of the first processing units of the first arrangement to perform computations of particular nodes of the third layer of the neural network; and

the at least a second subset of the first processing units is configured to receive the second activation output values from the memory and process the second activation output values according to the computations of the particular nodes of the third layer of the neural network.

2. The device of claim 1 , wherein the first and second subsets of the first processing units include one or more processing units also included in the second subset of the first processing units.

3. The device of claim 1 , wherein one of the first and second subsets of the first processing units includes one or more processing units not included in the other of the first and second subsets of the first processing units.

4. The device of claim 1 , wherein the neural network comprises a number of layers between the first and second layers, wherein the array comprises a number of arrangements between the first and last arrangements, and wherein the number of layers equals the number of arrangements.

5. The device of claim 1 , wherein the device includes a systolic processor chip, and wherein each of the first and last arrangements of processing units comprise circuitry embedded in the systolic processor chip.

6. The device of claim 1 , wherein the computations of a particular processing unit of the at least a first subset of the first processing units include a multiplication of input data with a weight.

7. The device of claim 6 , wherein the weight is stored locally at the particular processing unit of the first processing units.

8. The device of claim 6 , wherein the weight is retrieved from a memory external to the particular processing unit of the first subset of the first processing units.

9. The device of claim 1 , wherein the controller is further configured to maintain assignment of the at least a second subset of the first arrangement of processing units to perform the computations of the particular nodes of the third layer of the neural network during a first stage of back propagation.

10. The device of claim 9 , wherein the controller is configured to re-assign the at least a first subset of the first arrangement of processing units to perform the computations of the particular nodes of the first layer of the neural network during a second stage of the back propagation.

11. A method for performing computations of a neural network comprising at least first, second, and third layers, via an array of processing units including at least a first arrangement of first processing units and a last arrangement of second processing units, the method comprising:

assigning at least a first subset of the first processing units of the first arrangement to the first layer of the neural network;

assigning at least a subset of the second processing units of the last arrangement to the second layer of the neural network;

receiving input data for the neural network;

performing computations of particular nodes of the first layer of the neural network values by using the at least a first subset of the first processing units to process the input data to generate first activation output values;

performing computations of particular nodes of the second layer of the neural network using the at least a second subset of the second processing units to generate second activation output values;

sending the second activation output values to a memory;

re-assigning at least a second subset of the first processing units of the first arrangement to the third layer of the neural network;

accessing, by the at least a second subset of the first processing units, the second activation output values from the memory; and

performing computations of particular nodes of the third layer of the neural network using the at least a second subset of the first processing units.

12. The method of claim 11 , wherein the re-assigning comprises assigning one or more processing units of the at least a first subset to the third layer of the neural network.

13. The method of claim 11 , wherein the re-assigning comprises assigning one or more processing units not in the at least a first subset to the third layer of the neural network.

14. The method of claim 11 , wherein the neural network comprises a number of layers between the first and second layers, wherein the array comprises a number of arrangements between the first and last arrangements, and wherein the number of layers equals the number of arrangements, the method further comprising assigning the number of arrangements to corresponding ones of the number of layers.

15. The method of claim 14 , further comprising:

systolically pulsing the first activation outputs from the first arrangement to an adjacent arrangement of the number of arrangements;

at each of the number of arrangements, generating an additional set of activation outputs and pulsing the additional set of activation outputs to a next adjacent arrangement; and

at the last arrangement, receiving the additional set of activation outputs systolically pulsed from one of the number of arrangements adjacent to the last arrangement.

16. A non-transitory computer-readable medium storing computer-executable instructions that, when executed by at least one processor, cause the at least one processor to perform operations comprising:

identifying a neural network for processing by an array of processing units, the neural network including at least first, second, and third layers, and the array including at least a first arrangement of first processing units and a last arrangement of second processing units;

assigning at least a first subset of the first processing units of the first arrangement to perform computations of the first layer of the neural network;

assigning at least a subset of the second processing units of the last arrangement to perform computations of the second layer of the neural network;

providing input data for processing by the at least a first subset of the first processing units;

storing activation output values received from the last arrangement to a memory;

re-assigning at least a second subset of the first processing units of the first arrangement to perform computations of the third layer of the neural network; and

providing the activation output values from the memory to the at least a second subset of the first processing units.

17. The non-transitory computer-readable medium of claim 16 , the operations further comprising assigning at least one processing unit of the first arrangement to both the at least a first subset of the first processing units and the at least a second subset of the first processing units.

18. The non-transitory computer-readable medium of claim 16 , the operations further comprising assigning at least one processing unit of the first arrangement to one of the at least a first subset and the at least a second subset of the first processing units and not the other of the at least a first subset and the at least a second subset of the first processing units.

19. The non-transitory computer-readable medium of claim 16 , wherein the neural network comprises a number of layers between the first and second layers, wherein the array comprises a number of arrangements between the first and last arrangements, the operations further comprising assigning each of the number of arrangements to a corresponding one of the number of layers.

20. A computer-implemented method, comprising:

determining that a number of layers of a neural network exceeds a number of arrangements of processing units of a systolic processing chip;

for a first set of forward propagations through a first portion of the neural network, assigning a first arrangement of the number of arrangements to perform computations according to a first layer of the neural network;

providing an input for the neural network to the first arrangement to initiate the first set of forward propagations;

storing an output from the systolic processing chip in a memory;

for a second set of forward propagations through a second portion of the neural network, assigning the first arrangement to perform computations according to a different layer of the neural network;

providing the output to the first arrangement to initiate the second set of forward propagations;

for a first set of back propagations, assigning the first arrangement to back propagate first received values according to the different layer of the neural network; and

for a second set of back propagations, assigning the first arrangement to back propagate second received values according to the first layer of the neural network.

21. The computer-implemented method of claim 20 , further comprising:

determining that each of the number of layers of the neural network has been processed by the systolic processing chip; and

storing an additional output of the systolic processing chip in the memory as an output of the neural network.

22. A device for performing computations of a neural network comprising a number of layers, the device comprising:

a controller configured to:

determine that a number of layers of the neural network exceeds a number of arrangements of processing units of a systolic processing chip;

for a first set of forward propagations through a first portion of the neural network, assign a first arrangement of the number of arrangements to perform computations according to a first layer of the neural network;

provide an input for the neural network to the first arrangement to initiate the first set of forward propagations;

store an output from the systolic processing chip in a memory;

for a second set of forward propagations through a second portion of the neural network, assign the first arrangement to perform computations according to a different layer of the neural network;

provide the output to the first arrangement to initiate the second set of forward propagations;

for a first set of back propagations, assign the first arrangement to back propagate first received values according to the different layer of the neural network; and

for a second set of back propagations, assign the first arrangement to back propagate second received values according to the first layer of the neural network.

23. The device of claim 22 , wherein the controller is further configured to:

determine that each of the number of layers of the neural network has been processed by the systolic processing chip; and

store an additional output of the systolic processing chip in the memory as an output of the neural network.

Assignments (8)
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 1, 2018
From: FRANCA-NETO, LUIZ M.; CARGNINI, LUIS V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 047025/0089 →
Continuity (3)
Provisional Application 62628076 · Feb 8, 2018
Provisional Application 62627957 · Feb 8, 2018
Related Publication 20190244083A1 · Aug 8, 2019
Cited By (1)
US 12,688,147