Nonvolatile memory with encoding for foggy-fine programming with soft bits
A storage apparatus includes non-volatile memory cells formed on a memory die, each memory cell configured to hold bits of data, and a control circuit formed on the memory die. The control circuit is configured to calculate parity data for data to be stored in the memory cells and program the memory cells to first distributions. The control circuit is also configured to read the memory cells in the first distributions, recover the data from results of reading the memory cells in the first distributions combined with the parity data, and further program the memory cells from the first distributions to second distributions to store the data. In some cases, the recovered data may have a high bit error rate. To handle higher bit error rates, the use of soft bit data is incorporated into an encoded foggy-fine scheme.
1. A method, comprising:
receiving, by a memory device, a plurality of logical pages of data to be stored in a page of a Multi-Level Cell (MLC) memory;
calculating, by circuits of the memory device, parity data for the plurality of logical pages of data;
programming the plurality of the logical pages of data in the page of MLC memory in a foggy program operation such that memory cells of the page of MLC memory are programmed to first distributions;
reading the page of MLC memory while the memory cells are in the first distributions in a first read operation;
storing the plurality of the logical pages of data from results of the first read operation in latches of the memory device;
calculating hard bit values for the plurality of the logical pages of data by combining the results of the first read operation and the parity data within the latches of the memory device;
reading the page of MLC memory while the memory cells are in the first distributions in a plurality of second read operations; and
calculating, by circuits of the memory device, soft bit values for the plurality of the logical pages of data from results of the second read operations;
providing the hard bit values for the plurality of the logical pages of data and the soft bit values for the plurality of the logical pages of data to an error correction code (ECC) circuit of a non-volatile memory controller;
receiving from the ECC circuit a copy of the plurality of logical pages recovered from the hard bit values and the soft bit values; and
further programming the page of the MLC memory from the first distributions to second distributions in a fine programming operation, the second distributions representing the recovered plurality of logical pages of data.
2. The method of claim 1 , wherein calculating the soft bit values for the plurality of logical pages of data from the results of the second foggy read operations includes:
determining first intermediate soft bit values from results of a first set of the second foggy read operations;
determining second intermediate soft bit values from results of a second set of the second foggy read operations; and
determining the soft bit values from logical combinations of the first intermediate soft bit values and the second intermediate soft bit values.
3. The method of claim 2 , wherein:
the first set of the second foggy read operations is performed using a read value offset above a first voltage level and a read value offset below the first voltage level; and
the second set of the second foggy read operations is performed using a read value offset above a second voltage level and a read value offset below the second voltage level, the first voltage level and the second voltage level being distinct.
4. The method of claim 2 , wherein:
the first set of the second foggy read operations is performed using a read value offset by a first amount above a first voltage level and a read value offset by the first amount below the first voltage level; and
the second set of the second foggy read operations is performed using a read value offset by a second amount above the first voltage level and a read value offset by the second amount below the first voltage level, the first amount being different than the second amount.
5. An apparatus, comprising:
a control circuit configured to connect to one or more arrays of a plurality of non-volatile memory cells, each of the non-volatile memory cells configured to hold a plurality of bits of data, and comprising a plurality of latches, the control circuit configured to:
calculate parity data for a plurality of logical pages to be stored in the plurality of non-volatile memory cells;
program the plurality of logical pages to be stored into the plurality of non-volatile memory cells to first distributions;
perform a first read of the plurality of non-volatile memory cells in the first distributions to obtain an initial copy of the plurality of logical pages;
latch the initial copy into the plurality of latches;
combine the parity data and the initial copy within the plurality of latches to generate hard bit values for each of the plurality of logical pages;
perform a plurality of second reads of each of the plurality of non-volatile memory cells in the first distributions to obtain initial soft bit values for the plurality of logical pages;
latch the initial soft bit values into the plurality of latches;
combine the parity data and the initial soft bit values within the plurality of latches to generate soft bit values for the plurality of logical pages;
provide the hard bit values and the soft bit values to an error correction code circuit of a non-volatile memory controller;
receive from the error correction code circuit a copy of the plurality of logical pages recovered from the hard bit values and the soft bit values; and
further program the plurality of non-volatile memory cells from the first distributions to second distributions to store the recovered copy of the plurality of logical pages.
6. The apparatus of claim 1 , wherein the control circuit is further configured to program the plurality of non-volatile memory cells to the first distributions in a foggy program operation such that the first distributions have a first amount of overlap and program the plurality of non-volatile memory cells from the first distributions to the second distributions in a fine programming such that the second distributions are narrower than the first distributions and have an overlap less than the first amount of overlap of the first distributions.
7. The apparatus of claim 1 , wherein the control circuit includes: an error correction code circuitry configured to receive the hard bit values and the soft bit values, and generate the recovered data from the hard bit values and the soft bit values.
8. The apparatus of claim 5 , wherein the control circuit is formed on a control die, the apparatus further comprising:
a memory die including the one or more arrays of non-volatile memory cells, the memory die formed separately from and bonded to the control die.
9. The apparatus of claim 5 , wherein the control circuit is formed on a single die with the one or more arrays of the plurality of non-volatile memory cells.
10. The apparatus of claim 5 , wherein the control circuit is configured to determine the soft bit values by:
determining first intermediate soft bit values from results of a first set of the second reads of the non-volatile memory cells in the first distributions;
determining second intermediate soft bit values from results of a second set of the second reads of the non-volatile memory cells in the first distributions; and
determining the soft bit values from logical combinations of the first intermediate soft bit values and the second intermediate soft bit values.
11. The apparatus of claim 10 , wherein the control circuit is further configured to:
perform the first set of the second reads using a read value offset above a first voltage level and a read value offset below the first voltage level; and
perform the second set of the second reads using a read value offset above a second voltage level and a read value offset below the second voltage level, the first voltage level and the second voltage level being distinct.
12. The apparatus of claim 11 , wherein the logical combinations of the first intermediate soft bit values and the second intermediate soft bit values are additionally combinations of the parity data.
13. The apparatus of claim 11 , wherein the first voltage level and the second voltage level are voltage levels used to perform the first read of the plurality of non-volatile memory cells in the first distributions.
14. The apparatus of claim 11 , wherein one or both of (a) the offsets above and below the first voltage level and (b) the offsets above and below the second voltage level are asymmetric.
15. The apparatus of claim 10 , wherein the control circuit is further configured to:
perform the first set of the second reads using a read value offset by a first amount above a first voltage level and a read value offset by the first amount below the first voltage level; and
perform the second set of the second reads using a read value offset by a second amount above the first voltage level and a read value offset by the second below the first voltage level, the first amount being different than the second amount.
16. A non-volatile memory device, comprising:
a plurality of non-volatile memory cells each configured to hold a plurality of bits of data; and
one or more control circuits connected to the plurality of non-volatile memory cells, the one or more control circuits comprising:
means for calculating parity data for data to be stored in the plurality of non-volatile memory cells;
means for programming the data to be stored in the plurality of non-volatile memory cells to first distributions in a foggy program operation such that the first distributions have a first amount of overlap;
means for reading the plurality of non-volatile memory cells programmed to the first distributions;
means for latching results of reading the plurality of non-volatile memory cells programmed to the first distributions;
means for determining hard bit values for the data to be stored in the plurality of non-volatile memory cells by combining, within the means for latching, the results of reading the plurality of non-volatile memory cells programmed to the first distributions and the parity data;
means for reading the plurality of non-volatile memory cells in the first distributions to determine soft bit values for the data to be stored in the plurality of non-volatile memory cells;
means for providing the hard bit values for the data to be stored in the plurality of non-volatile memory cells and the soft bit values for the data to be stored in the plurality of non-volatile memory cells to an error correction code (ECC) circuit of a non-volatile memory controller;
means for receiving from the ECC circuit of a non-volatile memory controller recovered data to be stored in the plurality of non-volatile memory cells from the hard bit values and the soft bit values; and
means for further programing the plurality of non-volatile memory cells from the first distributions to second distributions to store the recovered data, wherein the second distributions have an overlap less than the first amount of overlap of the first distributions.