IP Library Granted Patent US 10,929,224
Granted Patent B2
US 10,929,224 · App. 16/447,861 · Granted Feb 23, 2021

Partial XOR protection

Inventors: Avi Klein (Tel Aviv, IL); Eran Sharon (Tel Aviv, IL); Gadi Vishne (Petach-Tikva, IL); Igor Genshaft (Bat Yam, IL); Marina Frid (Jerusalem, IL); Michal Silbermintz (Tel Mond, IL)
Assignee: Western Digital Technologies, Inc.
G06F11/1068G06F3/0616G06F3/0659G06F3/0679G11C29/52
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Quick Facts
Patent No.
US 10,929,224
App. No.
16/447,861
Granted
Feb 23, 2021
Kind
B2
Abstract

A system and method for applying a first level of protection to data in a memory module include identifying a weak wordline from at least one of a plurality of blocks of the memory module. Each of the plurality of blocks includes a plurality of wordlines. The system and method also include determining that the weak wordline is to receive the first level of protection and applying the first level of protection to the weak wordline.

Claims (51)

1. A memory device comprising:

a plurality of blocks of memory cells, wherein each of the plurality of blocks comprises a plurality of wordlines; and

a memory controller in communication with the plurality of blocks of memory cells, the memory controller configured to:

categorize the plurality of blocks of memory cells into a first pool of the blocks and a second pool of the blocks, wherein the second pool comprises suspected grown bad blocks of the plurality of blocks and the first pool comprises remaining blocks of the plurality of blocks that are not the suspected grown bad blocks;

apply a first level of protection to each of the plurality of wordlines of each of the suspected grown bad blocks in the second pool;

periodically monitor the remaining blocks of the memory module in the first pool for identifying an additional suspected grown bad block;

transfer the additional suspected grown bad block to the second pool; and

apply the first level of protection to each of the plurality of wordlines of the additional suspected grown bad block.

2. The memory device of claim 1 , wherein the memory controller is further configured to identify that a first block of the plurality of blocks is one of the suspected grown bad blocks or the additional suspected grown bad block based upon a parameter associated with the first block deviating from a predetermined threshold by a predetermined value.

3. The memory device of claim 1 , wherein the memory controller is further configured to combine a wear leveling mechanism with the first level of protection.

4. The memory device of claim 1 , wherein the memory controller is further configured to apply another protection to the remaining blocks of the memory module in the first pool.

5. The memory device of claim 4 , wherein:

the first level of protection includes XOR protection; and

the other level of protection does not include XOR protection.

6. A memory device comprising:

one or more memory modules, each of the one or more memory modules comprising a plurality of blocks, and each of the plurality of blocks comprising a plurality of wordlines; and

a memory controller associated with each of the one or more memory modules,

wherein the memory controller is configured to:

identify a group of wordlines in the one or more memory modules for XOR protection;

apply the XOR protection to the group of wordlines; and

periodically monitor a plurality of wordlines in the one or more memory modules for which the XOR protection is not applied to update the group of wordlines for which the XOR protection is applied.

7. The memory device of claim 6 , wherein the memory controller is further configured to apply a second protection to each of the plurality of wordlines to which the memory controller does not apply the XOR protection.

8. The memory device of claim 6 , wherein the memory controller is further configured to apply a wear leveling mechanism to the group of wordlines in addition to the XOR protection.

9. The memory device of claim 6 , wherein the group of wordlines to which the XOR protection is applied comprise first four wordlines of each of the plurality of blocks.

10. An apparatus, comprising:

a memory controller configured to connect to a plurality of blocks of non-volatile memory cells, wherein the memory controller is configured to:

apply a first level of protection to reduce risk of losing data to a set of one or more word lines in a first block of the plurality of blocks; and

apply a second level of protection to reduce risk of losing data to a plurality of wordlines in the first block that do not receive the first level of protection.

11. The apparatus of claim 10 , wherein the first level of protection includes XOR protection.

12. The apparatus of claim 11 , wherein the second level of protection does not include XOR protection.

13. The apparatus of claim 12 , wherein:

the second level of protection includes error correction code protection.

14. The apparatus of claim 10 , wherein:

the first level of protection includes XOR protection over a first stripe height; and

the second level of protection includes XOR protection over a second stripe height that is larger than the first stripe height.

15. The apparatus of claim 10 , wherein the memory controller is further configured to:

include the first wordline in the set in response to identification of the first wordline as a weak wordline.

16. The apparatus of claim 15 , wherein the memory controller is further configured to:

measure a value of a parameter from each of the plurality of wordlines in the first block;

compute an average value of the measured value from each of the plurality of wordlines in the first block; and

identify the first wordline as a weak wordline in response to the value of the parameter for the first wordline deviating from the average value of the parameter by a predetermined threshold.

17. The apparatus of claim 10 , wherein the memory controller is further configured to:

select at least one suspected grown bad block from the plurality of blocks;

identify a weak wordline from each of the at least one suspected grown bad block; and

place the at least one suspected grown bad block in a first pool and placing remaining ones of the plurality of blocks in a second pool.

18. The apparatus of claim 17 , wherein the memory controller is further configured to:

periodically monitor the remaining ones of the plurality of blocks in the second pool for identify an additional suspected grown bad block.

19. The apparatus of claim 18 , wherein the memory controller is further configured to:

transfer the additional suspected grown bad block to the first pool.

20. The apparatus of claim 10 , wherein the memory controller is further configured to:

designate a subset of the plurality of wordlines from each of the plurality of blocks as a weak wordline on which the first level of protection is applied.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2019
From: KLEIN, AVI; SHARON, ERAN; VISHNE, GADI; GENSHAFT, IGOR; FRID, MARINA; SILBERMINTZ, MICHAEL
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 050759/0379 →
Continuity (1)
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