Word-line inter-cell interference detector in flash system
View Patent ↗Read signals are obtained from memory cells, and a first read signal and a second read signal are identified, from among the plurality of read signals. The first read signal is associated with a first memory cell in a first word line and the second read signal is associated with a second memory cell in a second word line, and the second word line is adjacent to the first word line. An output for the first memory cell is generated, wherein the output is based on the first and the second read signals.
1. A method for retrieving information stored in flash memory, comprising:
obtaining a plurality of read signals from a plurality of memory cells;
identifying, from among the plurality of read signals, a first read signal associated with a first memory cell in a first word line and a second read signal associated with a second memory cell in a second word line, wherein the second word line is adjacent to the first word line; and
generating an output for the first memory cell, wherein the output is based on the first and the second read signals.
2. The method of claim 1 , further comprising:
decoding the first read signal based on the output.
3. The method of claim 1 , wherein the output is generated based on a trellis-based algorithm, the method further comprising:
determining one or more input values based on the second read signal; and
providing the determined one or more input values to the trellis-based algorithm, wherein the output is based on the provided input values.
4. The method of claim 3 , wherein the trellis-based algorithm references a trellis comprising a plurality of state transitions, each state transition representative of a transition of memory cell data levels that are read sequentially along the first word line, and each transition being associated with a respective one of the input values.
5. The method of claim 4 , wherein each of the input values is retrieved from one or more lookup tables based on an indexing of the one or more lookup tables by a first data level corresponding to the first read signal and a second data level corresponding to the second read signal.
6. The method of claim 5 wherein the first read signal is one of a predetermined number of bins associated with a predetermined density distribution curve associated with the first memory cell.
7. The method of claim 4 , wherein the trellis-based algorithm produces a log-likelihood ratio (LLR) or a posteriori probability (APP) for use by a decoder.
8. The method of claim 1 , further comprising:
identifying, from among the plurality of read signals, a third read signal associated with a third memory cell, the third memory cell being in the first word line and adjacent to the first memory cell, wherein the output is further based on the third read signal associated with the third memory cell.
9. The method of claim 8 , wherein the output is based on inter-cell interference data corresponding with a prior programming of the second and third memory cells.
10. The method of claim 1 , wherein the second word line is decoded before the first word line and the second read signal is a cell data level that is presumed to be valid.
11. A data storage system, comprising:
a decoder;
a plurality of memory cells; and
a controller coupled to the configuration memory and the plurality of memory cells, wherein the controller is configured to:
obtain a plurality of read signals from the plurality of memory cells;
identify, from among the plurality of read signals, a first read signal associated with a first memory cell in a first word line and a second read signal associated with a second memory cell in a second word line, wherein the second word line is adjacent to the first word line; and
generate an output for the first memory cell, wherein the output is based on the first and the second read signals.
12. The data storage system of claim 11 , wherein the controller is further configured to:
provide the output to the decoder; and
receive from the decoder, a decoded value for the first memory cell based on the output.
13. The data storage system of claim 11 , wherein the controller is further configured to:
generate the output based on a trellis-based algorithm;
determine one or more input values based on the second read signal; and
provide the determined one or more input values to the trellis-based algorithm, wherein the output is based on the provided input values.
14. The data storage system of claim 13 , wherein the trellis-based algorithm references a trellis comprising a plurality of state transitions, each state transition representative of a transition of memory cell data levels that are read sequentially along the first word line, and each transition being associated with a respective one of the input values.
15. The data storage system of claim 14 , wherein each of the input values is retrieved from one or more lookup tables based on an indexing of the one or more lookup tables by a first value corresponding to the first read signal and a second value corresponding to the second read signal.
16. The data storage system of claim 15 wherein the first read signal is one of a predetermined number of bins associated with a predetermined density distribution curve associated with the first memory cell.
17. The data storage system of claim 14 , wherein the trellis-based algorithm produces a log-likelihood ratio (LLR) or a posteriori probability (APP) for use by the decoder.
18. The data storage system of claim 11 , wherein the controller is further configured to:
identify, from among the plurality of read signals, a third read signal associated with a third memory cell, the third memory cell being in the first word line and adjacent to the first memory cell, wherein the output is further based on the third read signal associated with the third memory cell.
19. A computer program product tangibly embodied in a computer-readable storage device and comprising instructions that, when executed by a memory controller, cause the memory controller to:
obtain a plurality of read signals from a plurality of memory cells;
identify, from among the plurality of read signals, a first read signal associated with a first memory cell in a first word line, a second read signal associated with a second memory cell in a second word line, and a third read signal associated with a third memory cell, the third memory cell being in the first word line and adjacent to the first memory cell, the second memory cell being in the same bit line as the first memory cell, and the second word line is adjacent to the first word line; and
generate an output for the first memory cell, wherein the output is based on the first and the second and third read signals.
20. The computer program product of claim 19 , wherein the output is generated based on a trellis-based algorithm, wherein the instructions, when executed by the memory controller, further cause the memory controller to:
retrieve one or more input values from one or more lookup tables based on an indexing of the one or more lookup tables by a first value corresponding to the first read signal and a second value corresponding to the second read signal; and
provide the one or more input values to the trellis-based algorithm, wherein the output is based on the provided input values,
wherein the trellis-based algorithm references a trellis comprising a plurality of state transitions, each state transition representative of a transition of memory cell data levels that are read sequentially along a word line, and each transition being associated with a respective one of the input values.