IP Library Granted Patent US 10,884,663
Granted Patent B2
US 10,884,663 · App. 16/354,038 · Granted Jan 5, 2021

Executable memory cells

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Quick Facts
Patent No.
US 10,884,663
App. No.
16/354,038
Granted
Jan 5, 2021
Kind
B2
Abstract

A computing unit includes a data processing unit having a plurality of executable memory cells. Each of the plurality of executable memory cells includes a code portion for storing code, a data portion for storing data, and an arithmetic and logic unit for applying the code to the data. The computing system also includes a compilation unit for converting a sequence of instructions into an execution stream. The execution stream includes the code and the data that is executed by the plurality of executable memory cells.

Claims (52)

1. A method comprising:

compiling a sequence of instructions into an execution stream that comprises a plurality of pairs of interleaved code and data;

storing a first code of the execution stream in a code portion of a first executable memory cell;

storing a first data of the execution stream in a data portion of the first executable memory cell; and

applying the first code to the first data by a first arithmetic and logic unit of the first executable memory cell in a first operation.

2. The method of claim 1 , further comprising storing a result of the first operation within the code portion of the first executable memory cell.

3. The method of claim 1 , further comprising storing a result of the first operation within the data portion of the first executable memory cell.

4. The method of claim 1 , further comprising:

storing a second code of the execution stream in a code portion of a second executable memory cell;

transferring a second data from the second executable memory cell to the first executable memory cell; and

applying a third code of the execution stream to the first data and the second data by the first arithmetic and logic unit of the first executable memory cell in a second operation.

5. The method of claim 4 , further comprising storing a result of the second operation within the code portion or the data portion of the first executable memory cell.

6. The method of claim 4 , further comprising transferring a result of the second operation to the second executable memory cell.

7. The method of claim 1 , further comprising:

receiving, by a management unit of the first executable memory cell, the first code from the execution stream; and

storing, by the management unit, the first code in the code portion of the first executable memory cell.

8. The method of claim 1 , further comprising:

receiving, by a management unit of the first executable memory cell, the first data from the executable stream; and

storing, by the management unit, the first data in the data portion of the first executable memory cell.

9. The method of claim 1 , further comprising:

storing a second code of the execution stream in a code portion of a second executable memory cell;

combining the first code from the first executable memory cell and the second code from the second executable memory cell to obtain combined code; and

applying the combined code to the first data and a second data of the execution stream by the first arithmetic and logic unit of the first executable memory cell in a second operation.

10. The method of claim 1 , further comprising:

storing a second code of the execution stream in the code portion of the first executable memory cell; and

applying the second code to the first data by the first arithmetic and logic unit of the first executable memory cell.

11. A device comprising:

a data processing unit comprising a plurality of executable memory cells, each of the plurality of executable memory cells comprising:

a code portion for storing code;

a data portion for storing data; and

an arithmetic and logic unit for applying the code to the data; and

a compilation unit for converting a sequence of instructions into an execution stream,

wherein the execution stream comprises a plurality of pairs of interleaved code and data that are executed by the plurality of executable memory cells.

12. The device of claim 11 , wherein the compilation unit is a just-in-time compiler.

13. The device of claim 11 , wherein each of the plurality of executable memory cells further comprises a management unit for facilitating application of the code to the data via the arithmetic and logic unit.

14. The device of claim 11 , wherein a one operand operation is performed by a first executable memory cell of the plurality of executable memory cells.

15. The device of claim 11 , wherein a two operand operation is performed by a first executable memory cell and a second executable memory cell of the plurality of executable memory cells.

16. The device of claim 11 , wherein the data processing unit and the compilation unit are part of a host device.

17. A non-transitory computer-readable media including computer-executable instructions embodied thereon that, when executed by a data processing unit of a computing system, cause the data processing unit to perform a process comprising:

compiling a sequence of instructions into an execution stream that comprises a plurality of pairs of interleaved code and data;

storing a first code of the execution stream in a code portion of a first executable memory cell of the data processing unit;

storing a first data of the execution stream in a data portion of the first executable memory cell; and

applying the first code to the first data by a first arithmetic and logic unit of the first executable memory cell.

18. The non-transitory computer-readable media of claim 17 , wherein the process further comprises receiving the first code and the first data from the execution stream.

19. The non-transitory computer-readable media of claim 17 , wherein the process further comprises:

storing a second code of the execution stream in a code portion of a second executable memory cell of the data processing unit;

transferring a second data from the second executable memory cell to the first executable memory cell; and

applying a third code of the execution stream to the first data and the second data by the first arithmetic and logic unit of the first executable memory cell.

20. The non-transitory computer-readable media of claim 17 , wherein the process further comprises:

storing a second code of the execution stream in a code portion of a second executable memory cell;

combining the first code from the first executable memory cell and the second code from the second executable memory cell to obtain combined code; and

applying the combined code to the first data and a second data of the execution stream by the first arithmetic and logic unit of the first executable memory cell.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2019
From: DUBEYKO, VIACHESLAV; CARGNINI, LUIS VITORIO
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 048604/0270 →