IP Library Granted Patent US 10,991,879
Granted Patent B2
US 10,991,879 · App. 16/453,372 · Granted Apr 27, 2021

Multi-level phase change memory cells and method of making the same

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Quick Facts
Patent No.
US 10,991,879
App. No.
16/453,372
Filed
Jun 26, 2019
Granted
Apr 27, 2021
Kind
B2
Art Unit
2819
USPC
257/5
Abstract

A phase change memory cell includes a first electrode, a second electrode located over the first electrode, a vertical pillar structure located between the first and second electrodes, the pillar structure containing a first phase change memory (PCM) material portion, a second PCM material portion and an intermediate electrode located between the first PCM material portion and the second PCM material portion, and a resistive liner containing a first segment electrically connected in parallel to the first PCM material portion between the first electrode and the intermediate electrode, and a second segment electrically connected in parallel to the second PCM material portion between the intermediate electrode and the second electrode. The first PCM material portion has a different electrical resistance than the second PCM material portion, and the first segment of the resistive liner has a different electrical resistance than the second segment of the resistive liner.

Claims (20)

1. A memory device comprising at least one phase change memory cell, wherein the at least one phase change memory cell comprises:

a first electrode located over a substrate;

a second electrode located over the first electrode;

a pillar structure located between the first and second electrodes and extending along a vertical direction perpendicular to the substrate, the pillar structure comprising a first phase change memory (PCM) material portion, a second PCM material portion and an intermediate electrode located between the first PCM material portion and the second PCM material portion; and

a resistive liner comprising a first segment electrically connected in parallel to the first PCM material portion between the first electrode and the intermediate electrode, and a second segment electrically connected in parallel to the second PCM material portion between the intermediate electrode and the second electrode;

wherein:

the first PCM material portion has a different electrical resistance than the second PCM material portion; and

the first segment of the resistive liner has a different electrical resistance than the second segment of the resistive liner;

the electrical resistance along the vertical direction of a crystalline state of the second PCM material portion is x times the electrical resistance along the vertical direction of a crystalline state of the first PCM material portion, and x is greater than 1;

the electrical resistance along the vertical direction of the first segment of the resistive liner is y times the electrical resistance along the vertical direction of the crystalline state of the first PCM material portion;

y is greater than x, such that electrical resistance along the vertical direction of the first segment of the resistive liner is greater than the electrical resistance of the crystalline state of the second PCM material portion; and

the electrical resistance along the vertical direction of the second segment of the resistive liner is greater than the electrical resistance along the vertical direction of the first segment of the resistive liner.

2. The memory device of claim 1 , wherein:

electrical resistance along the vertical direction of the amorphous state of the first PCM material portion is n times the electrical resistance along the vertical direction of the crystalline state of the first PCM material portion; and

n is greater than y.

3. The memory device of claim 2 , wherein:

x is in a range from 1.5 to 20;

y is in a range from 1.5 to 400; and

n is in a range from 10 to 1,000,000.

4. The memory device of claim 2 , wherein the electrical resistance along the vertical direction of a first segment of the resistive liner located on the first PCM material portion is less than electrical resistance along the vertical direction of an amorphous state of the first PCM material portion, is less than electrical resistance along the vertical direction of an amorphous state of the second PCM material portion, and is greater than electrical resistance along the vertical direction of a crystalline state of the first PCM material portion.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 26, 2019
From: RUIZ, RICARDO; WAN, LEI; READ, JOHN; BAI, ZHAOQIANG; APODACA, MAC
To: WESTERN DIGITAL TECHNOLOGIES, INC.,
Reel/Frame 049597/0759 →